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Page Title: TRANSITION ENCODER/TIMING RECOVERY (TE/TR) CARD
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T.O. 31W-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3011
in the rate compare control circuit generates a load
strapped in the 1 position (fill bit quantity is greater than
signal that is applied to write address latch U25 and to
434 (refer to table 3-3)), AND gate U9-9 produces a low-
flip-flop U38 in the data compare logic. At the time that
level preset signal to J-K flip-flop U40-10 to inhibit the
the load signal is generated, the data bit associated with
diagnostic data compare function. During self-test, the
the write address written into the write address latch is
low output from AND gate U13-10 produces a low output
loaded into flip-flop U38. When the read address from
to OR gate U37-8 that, in turn, causes J-K flip-flop U40-6
the read address counter matches the write address in
to produce an error signal.
comparator U24, the A=B output from U24 is applied as
an enable signal through J-K flip-flops U29-10, U41-10,
5-203. TRANSITION ENCODER/TIMING RECOVERY
and U40-10 to AND gate U47. At the time that AND gate
(TE/TR) CARD.
U47 is enabled by flip-flop U40-10, the data bit in flip-flop
U38-9 and the data bit in flip-flop U38-6 are applied to
5-204. GENERAL.  The TE/TR card is one of the
exclusive OR gate U50-11. The two data bits should be
multiplexer channel cards that receives and processes
the same, therefore producing a low-level inhibit signal to
incoming digital data that are applied without associated
AND gate U47-3. AND gate U47-3, in turn, applies a
timing. The TE/TR card processes one of two types of
high-level signal to the K input of J-K flip-flop U40-6. J-K
incoming data: data with bit rates up to 400 bps using
flip-flop U40-6, in turn, applies a high-level signal to OR
transition encoding, or data whose bit rate is 75, 150,
gate U36-8. When there is a no compare from U50-11,
300, 600, 1200, 2400, 4800, or 9600 bps using timing
a low-level signal is applied to U36-8.
recovery. In the following discussion, the circuits on the
card are divided into three functions: timing recovery,
5-202. Timing activity detector U35-6 is held in
transition encoder, and rate comparison buffer (RCB).
conduction by the timing signals (TIXX) from timing
Figure 5-15 is a simplified block diagram that shows the
receiver No. 1. When the timing pulses are missing, the
two operational configurations in which the three
Q output from U35-6 goes low and inhibits the data bits
functions can be connected. The functional application
out of flip-flop U38-6. The low-level output from U35-6 is
of the card is selected by connecting the TE/TR
applied through AND gate U45-3 to enable AND gate
strapping switches to the TE or the TR positions.
U45-11. AND gate U45-11, in turn, presets J-K flip-flop
Incoming data with bit rates up to 400 bps are processed
U49-10 to inhibit a low-level error signal, caused by an
by the circuits that make up the transition encoder and
OOT condition, from being generated to OR gate U36-8
the RCB functions (switches strapped in the TE
when stuff comparator U48 detects an error condition
positions). The incoming data bit rate of 75, 150, 300,
and tries to set flip-flop U49-10. The Q output from U35-
600, 1200, 2400, 4800 or 9600 bps is processed by the
7 is applied through OR gate U37-8 to inhibit the low-
circuits that make up the timing recovery and the RCB
level error signal from J-K flip-flop U40-6 in the data
functions (switches strapped in the TR positions). The
compare function to OR gate U36-8. The high level
block diagram discussions are contained in paragraphs
signal from the Q output of U35-7 is also applied to OR
gate U31-4 to generate an out-of-tolerance signal
contain the detailed
OOTXX to the display card. When switch S1 is in the
URC position and switch position 9 of fill bit switch S2 is
5-50

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