Diagnostic Function

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

command (POS) applied to the decoder is decoded into

The data compare enable circuit, in turn, generates an

a positive stuff request that is routed to the output

enable signal to the data comparator when an address

selector. The output selector transmits a card diagnostic

compare is made and a gated clock signal MGCXX is

signal on the positive stuff request line (MPSTXX-)

present.

The enable signal applied to the data

during word 24 as described in the diagnostic functional

comparator is clocked by system clock signal MRIOX.

discussion. After word 24 occurs, the output selector

produces positive stuff request signal MPSTXX- when a

5-226. The data comparator actually performs a

positive stuff (POS) output is applied to it from the

random compare of one data in bit against one data out

decoder logic.

bit. Both bits being compared are from the same

address and should be of the same polarity. When the

5-223. Diagnostic Function (Figure 5-19).

bits being compared are not of the same polarity and an

enable signal is applied to the data comparator, an error

5-224. Data transition detector No. 2, first half detector

signal is generated and applied to the card error

No. 2, 2-bit shift register No. 2, and associated logic

detector.

duplicate the 3-bit code generated by the transition

encoder functional circuits.

The operation of the

5-227. The enable activity detector is held in conduction

duplicate transition encoding diagnostic circuits is the

by the enable signals from the data compare enable

same as that described for the equivalent functional

circuit. When the enable signals are missing, the

circuits. When the card uses the transition encoding

detector completes its duty cycle and applies a low-level

circuits, the 3-bit code data from the diagnostic circuits

error signal to the card error detector. The timing activity

are applied through switch S1, connected in the TE

detector is held in conduction by the appropriate TE or

position, to the data buffer. When the card uses the

TR timing signals applied through TE/TR switch S3.

timing recovery circuits, conditioned data from data

When the timing signals are missing, the detector

receiver No.2 are applied through switch S1, connected

completes its duty cycle and applies a low-level error

in the TR position, to the data buffer. The data (data in)

signal to the card error detector.

applied to the data buffer are clocked by its associated

timing signals to the data comparator. The data (data

5-228. The data in comparator compares the

out) from the data output buffer are also applied to the

conditioned data from data receivers No. 1 and No. 2.

data comparator.

When the data do not match, a low-level error signal is

applied to the card error detector.

5-225. The address comparator continually compares

the write address stored in the write address latch with

5-229. The card error detector, in turn, generates a card

the read address from the read counter in the RCB

error signal when any one of the four circuit error

functional circuits. When a compare is made, the A=B

conditions is detected. The card error signal from the

output from the address comparator is applied to the

detector is applied to the output selector, which, in turn,

data compare enable circuit.

generates the card error condition to the display card

during word 24.

5-57