Input-Output Data Rate Compare Function

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

by the incoming timing pulses associated with the

decoder logic, in turn, decodes the adder output to

incoming data, generates the 4-bit write addresses that

determine if a stuffing action is required, an out-of-

are applied to the data elastic storage register and to the

tolerance condition exists, or no action is required. The

write address latch. The read address counter is

decoder logic is configured so that, during a rate

sequentially incremented by the applied gated clock

compare, the offset between the write and read address

signals (MGCXX). The read address counter generates

is a predetermined count. Should the offset between the

the read addresses that are applied to a holding register

write address and the read address become greater than

and to the read address latch. The read addresses are

the predetermined count, a positive stuff (POS)

clocked out of the holding register to the elastic storage

command is decoded. If the offset between the write

address and the read address is less than the

out of the data elastic storage register are reclocked into

predetermined count, a negative (NEG) command is

the data output buffer by the system clock signal MRIO.

decoded.

When the offset variation between the

The data in the data output buffer are selectively

addresses is greater than the compensatory capability of

sampled by the GC/DM card.

the buffer function, an out-of-tolerance (OOT) command

is decoded. When the read address is effectively

5-220. Input-Output Data Rate Compare Function. The

tracking the write address (within tolerance), none of the

data and associated timing applied to the RCB circuit,

above commands are generated, indicating a no-action

are asynchronous to the multiplexer timing and can vary

condition.

+250 ppm from the multiplexer's nominal data rate. Any

variation of the applied data rate with respect to the

5-221. An out-of-tolerance (OOT) signal from the

multiplexer's data rate is detected and compensation is

decoder logic is a reset signal to the initialization logic.

initiated by this function. A rate compare is initiated

When the signal is applied to the initialization circuit, the

when a read address is loaded into the read address

circuit generates a reset signal to the read address

latch by the load signal applied from the initialization logic

counter and resets the counter to a count of 0. The

to the latch during bit 0 of word 24. At the same time, a

initialization logic also generates a preset signal, two

load enable signal is applied from the initialization logic to

clock times later, to the write address counter and

the rate compare control. With the load enable signal

presets the counter to a count of 10. The preset and

applied, the rate compare controller generates a load

reset signals are generated from the initialization logic

signal when the next timing signal from the timing

during word 24. The offset in count (normally a count of

receiver is applied. The load signal causes the write

8) between the two counters prevents them from

address latch to load in the write address from the write

generating identical read and write addresses to the

address counter. The load and load enable signals from

elastic storage register at the same time.

the initialization circuit are inhibited if an OOT signal is

generated by the decoder logic. The addresses in the

5-222. A negative stuff command (NEG) applied to the

two latches are applied to the B-C-1 adder, where the

decoder logic is decoded into negative stuff request

write address count is subtracted from the read address

signal MNSTXX- that is routed to the OEG card. In turn,

count to provide a 4-bit count to the decoder logic. The

a positive stuff

5-56