Diagnostic Function - TM-11-5805-688-14-10150

T.O. 31W-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

word counter to start counting at the beginning of the

5-199. Diagnostic Function.

next major frame. The word counter is incremented one

count each time signal MEOS3NX is generated and

5-200. Read and write address counters U4 and U7,

applied through inverters U53-2 and U53-4 to the CP

read and write address latches U5 and U6, B-C-1 adder

inputs of U28, U1, and U15. Before the circuits are

U12, and decoder logic U13 and U14 duplicate the rate

activated, 10 fill-bit strapping switches (0 through 9) are

compare functional circuits.

The out-of-tolerance,

strapped to a predetermined count that determines the

positive stuff, and negative stuff signals from decoder

number of gated clock pulses to be deleted during each

logic U13, U14 are applied to stuff comparator U48. The

major frame period. The 10-bit binary code from the fill-

output from U48 is normally a high level (A=B) signal that

bit switches is applied to the B inputs of 10-bit

holds the output from J-K flip-flop U49-10 high. When

comparator U21, U8. The 10 outputs from the word

the three outputs from decoder logic No. 1 and decoder

counter are applied in reverse sequence to the A inputs

logic No. 2 do not compare, the output from U48 goes

of the 10-bit comparator. This reverse sequence is

low, resulting in a low-level error signal from U49-10 to

performed to obtain a near-homogeneous output from

OR gate U36-9 in the input circuit of the output selector

the 10-bit comparator. Each time the reversed binary

circuit. An out-of-tolerance command from decoder logic

numbers applied to the A inputs of the comparator are

No. 1 is also applied to the out-of-tolerance generator

less than the programmed binary numbers applied to the

circuit consisting of J-K flip-flop U49-7 and one-shot

B inputs, a gated clock inhibit signal is generated.

multivibrator U44-6. The out-of-tolerance signal applied

Therefore, the gated clock inhibit signals from the

through inverter U46-10 causes U49-7 to go high and

comparator result in near-homogeneous low-level inhibit

trigger U44 into conduction. Thus the low-level output

inputs to AND gate U9-11. The result is gated clock

(OOTXX-) from U31-4 is generated for approximately 31

inhibit signals that occur (spread out) in a near-

seconds. The conditioned identical timing signals from

homogeneous sequence during each major frame

timing receiver U43-8 are applied to exclusive OR gate

period. Signals MW24NX and MEOS3NXtoggle flip-flop

U50-3 to exclusive OR gate U50-8. In normal operation,

U3-10 to set a one in shift register U10 during word 25.

exclusive OR gate U50-8 generates a low-level output

This causes U10 to generate an inhibit signal during

that is applied to inverter U46-8 and AND gate U47-6.

word 29 (count 5) that inhibits the word counter and AND

When a malfunction occurs, the output of exclusive OR

gate U36-6, thus preventing generation of a gated clock

gate U50-8 goes high and enables AND gate U47-6,

inhibit signal from being applied to AND gate U9-11

which, in turn, sets latch U52 that generates a low-level

during word 29. Activity detector U35-10 is held in

error signal to OR gate U36-13. The latch remains set

conduction by count 512 from the word counter when Ro

until reset signal ERST is applied through inverters U51-

is greater than 2 kbps. When Ro is less than 2 kbps,

8 and U51-10 to reset latch U52-6.

signal MEOS3NX holds U35-10 in conduction.

missing input causes the duty cycle of U35-10 to expire

5-201. A diagnostic data compare function is initiated

and generate an error signal to OR gate U36-8.

when AND gate U13-4

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