DETAILED CIRCUIT DISCUSSION. - TM-11-5805-688-14-10160

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

During the next TE timing signal, the output from J-K flip-

5-230. DETAILED CIRCUIT DISCUSSION.

flop U13-10 enables AND gate U19-11 to develop bit 3.

When the transition is a positive-going signal, the output

5-231. Transition Encoder Function.

from J-k flip-flop U13-10 is positive, and therefore the

output from AND gate U19-11 is low for a positive-going

5-232. Divide-by-N counter No. 1, U30, is a 4-bit binary

transition or is high for a negative-going transition. The

counter. The divide- by-4, -8, and -16 outputs of the

bits 1, 2, and 3 pulses are applied sequentially in time

counter produce the 225-Hz, 450-Hz, and 900-Hz

through OR gate U25-8 to the TE position of TE/TR

outputs that are applied to switch positions 75, 150, and

switch S2.

300 of TE range switch S5. The divide-by-4, -8, and -16

outputs of divide-by-N counter No. 2, U31, produce the

5-233. Timing Recovery Function.

300-Hz, 600-Hz, and 1200-Hz outputs that are applied to

switch positions 100, 200, and 400 of TE range switch

5-234. The conditioned data pulses from data receiver

S5. The selected timing signals applied through switch

U36-1 are applied to one-shot multivibrators U2-7 and

S5 are applied as TE timing signals, which are actually

U2-9. A positive-going or negative- going pulse applied

three times the desired data bit rate, to data sample flip-

to the two multi-vibrators triggers one of them into

flop U12. The conditioned data pulses from data

conduction for approximately 100 nanoseconds to

receiver U36-1 are applied to exclusive OR gate U18 and

develop a negative pulse that is applied through OR gate

J-K flip-flop U12-6. When a transition of a data pulse

U21-3 and inverter U3-2 as a reset signal to the 2

occurs, the output of exclusive OR gate U18-8 goes

counter stages.

The 9.8304-MHz timing signals

high. If the transition occurs during the first half of the

developed by crystal controlled oscillator Q1 are applied

TE timing signal, a high-level signal is clocked through

through amplifier Q3 to the clock inputs of binary

U1-10 to U1-6. If the transition occurs during the second

counters U4, U5, and U1l in the 2 counter circuit. The

half of the TE timing signal, the appropriate high- level or

divided down count from binary counter U4 (614.4 kHz)

low-level signal is clocked through J-K flip-flop U12-6.

is applied to binary counters U5 and U11 that provide the

This condition places matching input levels to exclusive

eight selectable outputs shown in figure 5-17. The

OR gate U18-8, resulting in a continued low-level signal

frequency range selected by TR range switch S9 is

being applied to J-K flip-flop U1-10. When J-K flip- flop

applied to binary counter U10. The divide-by-16 output

U12-6 is clocked, exclusive OR gate U18-11 has a high

of binary counter U10 is applied to J-K flip-flop U29,

output for one TE timing pulse, until J-K flip-flop U12-10

whose output completes a divide by 32 of the signals

is clocked by the next TE timing signal. The high-level

applied through switch S9. The counters continuously

bit 1 pulse from exclusive OR gate U18-11 is applied to

count and produce a timing signal, at the selected

J-K flip-flop U13-6 in the 2-bit shift register. The next TE

frequency range, between 75 bps and 9600 bps. Each

timing signal clocks the pulse through J-K flip- flop U13-6

time the transition detector generates a reset signal to

to enable AND gate U19-8 so that bit 2 from J-K flip-flop

the counters, and the timing pulse from J-K flip-flop U29-

U1-6 is applied to OR gate U25-8. If the data pulse

lb is

transition occurred during the first half of the TE timing

signal, the output from the AND gate is a low-level pulse.

5-59