Rate Conversion Buffer (RCB) Function.

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

synchronous with the incoming data pulse, no apparent

read address into read address latch U45 at the same

shift in the phase of the timing pulse in relationship to the

time. The addresses in the two latch circuits are applied

data pulse will occur. If the timing pulse from the J-K flip-

to B-C-1 adder U40. In turn, U40 produces an output to

flop is slightly out of synchronization with the timing pulse

the decoder logic, which produces a no-action, out-of-

transition, the resetting of the binary counters effectively

tolerance, positive stuff, or negative stuff signal. An out-

shifts the timing output from J-K flip-flop U29 so that the

of-tolerance decode from the decoder logic results in a

timing pulse performs a center sample of the incoming

low- level reset signal from AND gate U39-10 that is

data pulse.

applied to J-K flip-flop U35-10 to reset the initialization

circuit. A negative stuff decode is applied from AND gate

5-235. Rate Conversion Buffer (RCB) Function.

U41-8 and, through inverter U46-12 as signal MNSTXX-,

to the display card. A positive stuff decode is applied

5-236. The basic operation of the RCB functional

from AND gate U41-11 to the output selector (AND/OR

circuits is basically the same as that described for the

gate U22) and is transmitted as signal MPSTXX- to the

RCB card in paragraph 5-166. TE/TR switches S2 and

display card. The output selector circuit inhibits a

S3 are set to receive the applied data and associated

positive stuff signal during word 24 in each minor frame.

timing signals from the transition encoder or timing

recovery function. The applied data through switch S2

are clocked through data buffer U29-6 to data elastic

5-238. Diagnostics Function.

registers U27 and U28 by the timing signals applied

through switch S3. The write address is applied to the

5-239. The card error detector (OR gate U17) produces

data elastic registers for writing the data into the RCB

a card error signal to output selector U22 when any one

function. The read address counter is clocked by gated

of four error signals is applied to it. The output selector,

clock pulses MGCXX from the GC/DM card and are

in turn, transmits the error signal as signal MPSTXX-

applied through inverters U47 to the counter. The data

when word 24 bit 0 signal MW24NX- is applied from the

are clocked out of the elastic registers by holding register

OEG card.

U26, which, in turn, is clocked by system clock signal

MRIOXX. The data read out of register U27 or U28 are

5-240. Timing activity detector U8-6 is a one-shot

applied through AND/OR gate circuit U22 to output data

multivibrator that is held in conduction by the TE or TR

buffer J-K flip-flop U2-7. The channel data out signals

timing signals applied through TE/TR switch S3. When

(MDTOXX) are clocked out of the flip-flop by system

the timing signals are missing, the multivibrator

clock signal MRIOX and are routed to the GC/DM card.

completes its duty cycle and applies an error signal to

the card error detector.

5-237. The initialization logic (U42-11) produces an

enable signal that sets latch U43-11 in the rate compare

5-241. The data-in comparator (exclusive OR gate U18-

control during word 24. The rate compare control, in

6) normally produces a low-level signal, since the

turn, applies a load signal that latches the present write

conditioned data pulses from data receivers U36-8 and

address into write address latch U33. The initialization

U36-1 are identical. When the data pulses do not

circuit also applies a load signal that latches the present

compare,

Change 2 5-60