VOICE ENCODER (VE) CARD - TM-11-5805-688-14-10162

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

the high-level signal from the exclusive OR gate is

features in the output data pulse circuits.

applied through inverter U37-2 as a low-level error signal

to the card error detector.

5-244. The enable activity detector is a one-shot

multivibrator (U8-6) that is held in conduction by the A=B

5-242. Data transition detector No. 2 (U6-6), first half

enable signals from J-K flip-flop U14-6. When the

detector No. 2 (U6-9), and 2-bit shift register No. 2 (U7-6

enable signals are missing, the multivibrator completes

and U7-10) duplicate the transition encoder functional

its duty cycle and applies an error signal to the card error

circuits and produce 3-bit coded outputs from OR gate

detector.

U25-6 that are identical to the 3-bit coded outputs from

OR gate U25-8. The data pulses are applied through

5-245. VOICE ENCODER (VE) CARD.

TE/TR switch S1 and exclusive OR gate U15-11 to data

buffer U9-10. The data pulses are clocked out of the

5-246. GENERAL. The VE card is the channel option

data buffer by its associated timing to exclusive OR gate

card that services one incoming voice channel. The VE

U15-8 in the data comparator circuit, AND gate U21-11,

card receives the voice signals and encodes the signals

and J-K flip-flop U23-10. The output data pulses from

into synchronous digital data that are eventually

output data buffer U23-7 are also applied to one input of

multiplexed into the multiplexer's serial digital data

exclusive OR gate U15-8. And gate U21-11 receives an

output.

enable signal to pin 12 when the addresses for the two

data inputs to the OR gate are the same as described in

5-247. BLOCK DIAGRAM DISCUSSION (Figure 5-20).

paragraph 5-253. In effect, exclusive OR gate U15-8

together with AND gate U21-11 perform random

5-248. The incoming voice signals (DIXX) are applied

samples of one set of data bits at a time. When the two

through a bandpass filter circuit to filter out the out-of-

data bits applied to exclusive OR gate U15-8 are not

band signals that could affect the encoder circuits.

alike for a matched set of addresses, a low-level error

Filtering is accomplished by the attenuation of all signals

signal is applied from AND gate U21-11 to J-K flip-flop

below 140 Hz and above 5.0 kHz by at least 3 dB. The

U23, which, in turn, produces an error signal to card

filtered signals from the bandpass filter are one of two

error detector U17.

signal voltages applied to a voltage comparator.

Reconstructed analog signals from an integrator are the

5-243. Address comparator U32 produces an A=B

other voltages applied to the comparator.

output to J-K flip-flop U44-10 in the data compare enable

circuit when the write address and read address are the

5-249. In normal operation, the encoder circuits try to

same. The A=B signal is clocked from U44-10 and is

make the reconstructed analog signals duplicate the

applied to J-K flip- flop U14-10 by gated clock signal

incoming filtered audio signal. Since exact duplication is

MGCXX from the GC/DM card. The A=B signal is then

never achieved, the comparator produces a continuous

clocked through J-K flip-flops U14-10 and U14-6 by

error (delta) output signal, which, in turn, manipulates the

system clock MRIOXX and is applied as an enable signal

generation of the reconstructed analog signals and the

to AND gate U21-11. The two-clock delay provided by

the flip-flop circuits compensates for delay due to design

Change 2 5-61