BLOCK DIAGRAM DISCUSSION - TM-11-5805-688-14-10164

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

derived digital outputs. In normal operation, the encoder

circuits continuously change the reconstructed analog

exceeds the reconstructed analog signal voltage level.

signals to minimize the voltage differences between the

The high-level or low-level dc voltages from the

two signal voltage levels applied to the comparator. It is

comparator are clocked as digital ones or zeros into the

from this error signal that the digital representation for

3-bit data shift register by gated clock pulses MGCXX

the analog signals is developed as described in the

from the GC/DM card. Bit 1 from the first stage of the

discussion that follows.

shift register is sampled and clocked through the output

data buffer by multiplexer system clock signals MRIOX-.

5-250. The decoder logic samples the three bits in the

Bit 1 is also applied as an enable or inhibit control signal

3-bit shift register for a condition whereby all the outputs

to the negative inhibit switch and the positive inhibit

are ones or zeros. When the condition exists, the

switch.

integrator has been driven in the same direction for the

last three clock times (MGCXX). At this time, the

5-253. The decoder logic generates a boost enable

decoder logic generates an enable signal to the

signal to the slope control when it decodes three

integrator control circuit.

consecutive zeros or ones from the 3-bit shift register. A

series of three consecutive ones or zeros indicates that

5-251. The integrator control circuit provides a positive

the integrator has been driven in one direction for three

or negative drive signal to the integrator. The integrator,

consecutive clock times (MGCXX).

The condition

in turn, generates the integrated signal that is

normally occurs when high amplitude audio signals or

representative of the incoming analog signal. The

high frequency audio signals are being encoded and the

integrated signal is subject to constant correction in order

output of the integrator is unable to decrease the

to decrease the delta voltage between the incoming

amplitude of the error voltage between the filtered audio

signal and the integrated signal. Figure 5-21 shows a

signal and the reconstructed analog signal. Therefore,

typical input audio signal and the integrated signal

when three consecutive ones or zeros are detected by

developed and applied to the comparator.

The

the decoder logic, the boost enable signal is generated to

integrated signal is subject to constant positive or

increase the drive voltage from the slope control. Thus,

negative signal correction in an attempt to continually

an increased (greater slope) output from the integrator is

decrease the delta voltage output that results from the

obtained so that the error voltage between the two

constant signal comparison.

signals can be minimized.

5-252. A continuous series of high- level or low-level

5-254. The slope control generates the drive voltage

error signal outputs from the comparator is applied to the

that determines the slope of the output signal from the

first stage of a 3-bit shift register.

When the

integrator. The negative drive voltage from the slope

reconstructed analog signal voltage level exceeds the

control is applied to an inverter and to the negative inhibit

voltage level of the applied filtered audio signal voltage, a

switch. The inverted output from the inverter is applied

high level dc voltage is effectively generated from the

as a positive drive

comparator and is applied to the 3-bit shift register. In

turn, a low-level output is generated and applied to the

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