Digital Processor Test Set CPU Control Function.

TM 32-5811-024-14&P

b. Detailed Description. Oscillator U3 provides a 500-kHz square wave (test point A) applied to RF simulator CCA

A2 via buffer U5A and to select code generator U29.

U29 is a counter that produces a binary 0-to-7 count at its output pins (QA, pin 14; QB, pin 13; and QC, pin 12). This

binary output is applied to multiplexer buffers U31A, U31B, and U31D and to select decoder U28.

The binary output of U29 applied to multiplexer buffers U31A, U31B and U31D produces the respective MUX0,

MUX1, and MUX2 data word select output (see figure 5-1). This negative true binary output addresses the display

multiplexer CCA of the unit-under-test digital processor. The display multiplexer CCA responds by providing eight 8-bit

data words, one at a time, according to the binary select code (MUX0, MUX1, and MUX2) output. Table 5-2 lists and

describes the eight data words obtained from the unit-under-test display multiplexer.

The binary output of U29 applied to select decoder U28 produces a load clock that transfers the incoming data

word bits to the appropriate display storage latch. U28 is a binary-to-decimal decoder that responds to binary select code

generator U29 output by producing eight staggered load clocks. These clocks coincide with the arrival of a

corresponding 8-bit data word (DM0 thru DM7) from the unit-undertest display multiplexer. The incoming data word bits

are inverted by U21 and U18 to provide positive true data that are loaded into the respective display storage latch by

corresponding load clocks. The output of the display storage latch provides direct drive to the binary and octal LED

displays on processor display CCA A1.

5-9. Digital Processor Test Set CPU Control Function.

a. General. The digital processor test set provides the means to externally control the unit-under-test digital

processor (CPU). In addition to starting and halting the CPU, manipulation of the digital processor test set front-panel

switches allows the operator to bypass the operational instruction memory (the program ROMs of the CPU) and use

digital processor test set diagnostic ROMs in its place.

The operator can also preset a digital processor starting address and the halting address (breakpoint address).

b. Detailed Description. The typical digital processor control sequences listed in table 5-3 describe digital processor

test set and unit-under-test digital processor circuit activity in response to digital processor test set front-panel switching.

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