Section III. DETAILED THEORY OF OPERATION

TM 32-5811-024-14&P

Table 5-1. Card Cage Assembly CCA Functions - Continued

CCA

Function

Transceiver/Test

module. CCA A10 generates a pseudorandom (PR)

CCA A10 (continued)

coded data stream from the transceiver I/O module

in response to a 5-kHz XMIT clock. This PR output

simulates XMIT data. The transceiver I/O module uses

the XMIT data as a test signal while undergoing different

test configurations in response to digital processor

test set front-panel TRANSCEIVER CONTROL switching.

Diagnostic ROM

Contain 1024 24-bit diagnostic instruction words/each.

CCAs All and A12

These words are applied to the unit-under-test digital

processor in response to a 16-bit RADO thru RAD15

address word received from the unit under test. Diag-

nostic buffer CCA A4 buffers the input address as well

as the output instruction word. These diagnostic ROM

output words replace the unit-under-test digital pro-

cessor ROM outputs when the digital processor test set

front-panel NORM ROM/DPTS ROM switch (A3S1) is in the

DPTS ROM position.

Section III. DETAILED THEORY OF OPERATION

5-7. General.

This section provides detailed circuit theory for the digital processor test set. Figures FO-7 thru FO-17 are schematic

diagrams of digital processor test set CCAs.

5-8. Display Storage Function.

a. General. (See figure FO-9) Display storage CCA A3 performs the following functions:

(1) Addresses the unit-under-test display multiplexer CCA to access unit-under-test digital processor bus data.

(2) Sorts and stores the bus data obtained from the unit-undertest digital processor to provide drive to LEDs

on processor display CCA A1.

(3) Generates a 500-kHz clock for use by RF processor simulator CCA A5.

5-5