SEQUENCER (SEQ) CARD - TM-11-5805-688-14-10167

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

1 of U1-12. This results in a decreased drive voltage to

minor frame equals PS signal is generated and applied

integrator U4-12, thus decreasing the slope of the

to the GC/DM card during each minor frame period that

reconstructed analog signal applied to the integrator

is designated to perform an overhead service function for

circuit.

a selected used port. Paragraphs 5-267 through 5-289

contain the block diagram discussions based on figure

5-264. Diagnostic Function. Transistors Q4 and Q6 are

FO-3. Paragraphs 5-290 through 5-305 contain the

normally cut off and transistor Q5 is conducting. When

detailed circuit discussion based on the seq card logic

an error condition is detected, either transistor Q4 or Q6

diagram in the circuit diagrams manual.

is forced into conduction and biases Q5 off. This

condition causes Q5 to change from a low input to a high

5-267. BLOCK DIAGRAM DISCUSSION (Figure FO-

input to inverter U9-8. Inverter U10-11 holds a low-level

3).

inhibit to inverter U9-8 at all times except during word 24.

Word 24 signal MW24NX- produces a high-level enable

5-268. General.

output from inverter U10-11 to inverter U9-8 during word

24 and permits Q5 to generate a high-level error signal

5-269. In the following discussions, the circuits on the

to the inverter when an error is detected on the card.

sequencer card are divided into three functions: write,

Transistor Q5 is biased off to generate the high-level

read, and diagnostic. Before the equipment is initially

error signal when a voltage change to the base of Q4

placed in operation, two sets of switches on the card, the

and Q6 is greater than 5 volts. This occurs when an

PORT STRAPPING switches and the PORTS IN USE

switches, are strapped to a selected system

operational amplifier malfunctions or when a logic circuit

configuration.

The PORT STRAPPING switches

malfunctions and causes one or more of the operational

effectively identify the active data channels and the used

amplifiers to saturate in one direction. The outputs of

ports associated with each channel. The PORTS IN

operational amplifier U2-10, U2-12, and U4-12 provide

USE switches identify the maximum number of ports

the diagnostic sample voltages to the base of Q4 and

used in a system configuration.

Q6. In turn, a high level input to inverter U9-8 during

word 24 produces the low-level error indication using

5-270. Each of the 31 PORT STRAPPING switches

signal MPSTXX-.

represents a port location. A used port representing an

active channel is strapped to the A input, and each

5-265. SEQUENCER (SEQ) CARD.

additional used port associated with an active channel is

strapped to the S input. Electrically, an A strapped port

5-266. GENERAL. The seq card is one of the common

is a binary one (+5 vdc) and an S strapped port is a

card types in the multiplexer set.

Three major

binary zero (ground). Port 1 is assigned active channel 1

multiplexer timing. and control signals are generated by

and is hardwired in the A strapped configuration. Ports 2

the seq card: the end-of-scan signals, which identify the

through 31 can be strapped to designate up to an

end of each word period, are applied to the GC/DM and

additional 14 active channels, together with their

OEG cards; channel address signals, which select the

associated used ports. Each system configuration uses

active channel to receive a gated clock signal, are

a minimum of 15 ports; additional strapping of ports 16

applied

the

GC/DM

card;

the

through

Change 1 5-66