DETAILED CIRCUIT DISCUSSION - TM-11-5805-688-14-10176

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

applied to the channel address comparator. In normal

the counts are equal, an A=B signal is applied from U34

operation, the channel addresses should compare and

to flip-flop U21-6 in the end-of-scan register circuits. The

produce an A=B output from the comparator. The A-B

Q output from flip-flop U21-6 produces end-of-scan

output is applied through inverter U31 and inhibits AND

signal DEOS- when the next system clock signal MRIO

gate U39. The inhibit signal applied to AND gate U39

occurs. In turn, the Q output from U21-5 is a high input to

flip-flop U21-9. The Q output from U21-7 goes low when

from the write/read controller is generated every other

the next system clock signal MRIO occurs. The low

scan time (EOS2 to EOS2). Therefore, an error signal is

signal presets write port address counter U9, U22 and

developed and applied to OR gate U47A when the

active channel counter U16, and clears read port

channel addresses are not the same and the inhibit

address counter U36, U43. The Q output from U21-7

signal to AND gate U39 is not present. The operation of

also inhibits AND gate-U37-3 in the read reset generator.

the out-of-sequence flip-flop and the write/read controller

The Q output from U21-9 is applied to flip-flop U33-9 to

is the same as that described in paragraph 5-287.

generate end-of-scan signals MEOS2B and MEOS2B-.

The Q output from U21-9 is also applied to flip-flop U33-

5-290. DETAILED CIRCUIT DISCUSSION.

5, which generates end- of-scan signal MEOS2 that is

applied to flip-flop U40-5 in the write/read control circuit.

5-291. Write Function. Port scan counter U2, U3 is

The Q output from U33-6 is applied as a clock signal to

incremented by system clock signals MRIO applied

flip-flop U32-9 in the write/read control circuit.

through inverters U4 and US5. At the end of each scan

(EOS to EOS), the counter is preset to a count of one by

5-292. Write port address counter U9, U22 is

end-of-scan signal DEOS- from flip-flop U21-6 in the

sequentially incremented by system clock signals MRIO.

end-of-scan register circuits. The counter sequentially

The 5-bit write port address from U9, U22 is applied

generates one 5-bit port address (signals S1, S2, S4, S8,

through read/write port address selector U10, U23 to

and S16) for each used port in the system configuration.

R.A.M. U18, U19 during the write function. Each time

Each port read address causes active port multiplexer

system clock signal MRIO and the write enable signal

US, U27 to interrogate one of the PORT STRAPPING

from the write/read control circuit are applied to AND

switch positions. Each PORT STRAPPING switch set in

gated U39-3, the 4-bit binary channel address in the

the A position causes a low output from U8 or U27 to be

active channel counter is written into the R.A.M.

applied to OR gate U15-6 to produce a high input to flip-

flop U29. In turn, each high input to U29 increments

5-293. When the equipment is turned on, the channel

active channel counter U16 one count. Therefore, during

addresses-read out of the functional R.A.M. are not the

one complete scan, or word time, counter U16 is

same as the channel addresses read out of the

incremented to a count that equals the number of active

diagnostic R.A.M. over a given period of time, since the

channels in the configuration. In turn, a complete word

circuits have a random start. Therefore, when channel

or scan time is obtained when the port address from

address comparator U20 does not produce an A=B

counter U2, U3 that is applied to ports-in-use comparator

signal

during

compare

U34 is equal to the ports-in-use count that is applied to

U34 from the PORTS IN USE switches. At the time that

5-75