DETAILED CIRCUIT DISCUSSION-CONT. - TM-11-5805-688-14-10177

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

time, the write/read control circuits generate a write

minor frame count signals (MMFCO through MMFC3)

enable signal to the functional write circuits for one scan

are applied to the A inputs of U42. Exclusive OR gate

time. Once the channel addresses are correctly written

U28- 8 processes the MSB (MMFC4) of the 5-bit channel

into the two R.A.M.'s, the channel address comparator

address. Comparator U42 processes the other four bits.

produces A=B signals in a no-error condition. In turn, the

Each time the channel address applied to U42, U28 is

write/read control circuits inhibit the write mode until a

the same as the minor frame count, an A=B (high) signal

no-compare condition is detected by U20. The operation

is generated from U42 to AND gate U47-6, and a low

of the write/read control circuits is described in

signal is generated from U28-8 and is applied through

paragraph 5-298.

inverter U31-6 to AND gate U47-6; Therefore, AND gate

U47-6 produces a low output during word 28 when a

5-294. Read Function. The 5-bit read port address

compare is made. The signal is applied through inverter

from read port address counter U36, U43 is applied to

U31-4 to produce signal MMF=PS.

N+1 adder U44 and to minor frame equals port

sequence comparator U28, U42. The port address from

5-296. Read/write port address selector U10, U23

U36, U43 is also applied, with the weights of the binary

applies a write address to R.A.M. U18, U19 in the write

bits reversed, to read/write port address selector U10,

mode each time a write enable (high) signal is applied

U23. The output from U44 is applied to the A inputs of

from the Q output of flip- flop U32-8. In turn, a read

read ports-in-use comparator U35. At this point, the

enable (low) signal is applied from the Q output of U32-8

weights of the binary bits are again reversed to their

to U10, U23 in the read mode, allowing the read address

original value to produce the same address (plus one)

to be applied to the R.A.M. The write or read enable

that is applied to U10, U23. When the address from U35

signal that is applied through AND gate U39-3 to the

is greater than the fixed binary count from the PORTS IN

R.A.M. is controlled by the Q output from flip-flop U32-9.

USE switches, an enable signal is applied to one input of

During the read mode, the 4-bit binary channel address

AND gate U37-3 in the read reset generator circuit. The

in the selected R.A.M. address is read out of the QO

termination of end-of-scan signal enables U37-3 and a

through Q3 outputs of R.A.M. U18, U19 to the four

high is applied from OR gate U37-6 to flip-flop U29-7.

associated reclocking flip-flops (U25-5, U25-9, U26-5,

When U29-7 is clocked and a high is applied from

and U26-9). The Q outputs of the four reclocking flip-

inverter U45-4, AND gate U37-8 applies a low load signal

flops produce the four output channel address signals

to U36, U43. This causes counter U36, U43 to skip the

MCHAD1, MCHAD2, MCHAD4, and MCHAD8.

next sequential count since the count preset into the

counter is equal to the existing count plus two. This

5-297. The Q outputs of the four reclocking flip-flops are

function prevents the counter from generating a port

applied to the A inputs of channel address comparator

number that is higher than the highest number of used

U20. The four channel address signals generated in the

ports in the system configuration.

channel address diagnostic circuits are applied to the B

inputs of U20. In normal operation, an A=B output from

5-295. Each 5-bit channel address from the read port

U20 is applied through inverter U31-8 as an inhibit signal

address counter is also applied to the B inputs of minor

to one input of AND gate U39-6.

frame equals port sequence comparator U42, U28. The

5-76