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 T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3010
When a no-compare is detected in U20, the inhibit signal
The write cycle is completed when the next end-of-scan
to AND gate U39-6 becomes an enable signal, The Q
signal sets the Q output of U32-9 low to inhibit AND gate
output from flip-flop U32-6 in the write/read control circuit
U39-3 in the R.A.M. input. At this time, U39-3 applies
goes high every other time end-of-scan signal MEOS2 is
the read enable signal to the R.A.M. The high Q output
generated. The high Q output enables the other input to
from U32-8 enables the read address input to the
AND gate U39-6. At the time that both inputs to U39-6
read/write port address selector.
are high, a low error signal is applied to OR gate U47-12
to produce a high input to flip-flop U40-9 in the write/read
control circuits. This condition causes the write/read
5-299. Flip-flop U40-5 in the write/ read control circuit is
control circuits to initiate a write mode.
toggled by end-of-scan signal MEOS2 from flip- flop
U33-5. This flip-flop produces the read and write enable
5-298. Write/Read Control Circuit. Flip-flop U40-9,
signals to the channel address diagnostic circuits. When
together with flip- flop U32-9, produces a write enable
the Q output of U40-5 is high, one input of AND gate
signal to read/write port address selector U10, U23 and
U39-11 is enabled and a write enable signal is applied to
to R.A.M. U18, U19 when the output from OR gate U47-
R.A.M. U12, U13 each time system clock signal MRIO-
12 is high. The output from OR gate U47-12 is forced
occurs. In turn, the low Q output from U40-5 enables the
high by one of three conditions: (1) when the functional
write address input to read/write port address selector
and diagnostic channel addresses are not the same, (2)
U11, U23. At the same time, the Q output from flip-flop
when end-of-scan signal MEOS2 is missing, and (3)
U32-6 is a low inhibit input to one input of AND gated
when error signal PSERR- is generated. A high output
U39-6, which inhibits channel address comparator U20
from OR gate U47-12, together with system clock signal
when the channel address diagnostic circuits are in the
MRIO, produces a high Q output from U40-9 to flip-flop
write mode. When the next end-of-scan signal toggles
U32-9. When the next end-of-scan signal from flip-flop
U40-5, the channel address diagnostic circuits switch to
U33-6 is applied to U32-9, the Q output from U32-9 goes
the read mode. In turn, the Q output from U32-6 enables
high and enables one input of AND gate U39-3 in the
the channel address comparator. Therefore, channel
R.A.M. input. In turn, U39-3 enables the write input of
address comparator U20 is inhibited during the write
the R.A.M. each time system clock signal MRIO- occurs.
mode to prevent an erroneous no-compare from U20.
The low Q output from U32-8 enables the write address
input of read/write port address selector U10, U23. The
5-300. Diagnostic Circuits.
As described in the
Q output from U32-8 also presets flip-flop U32-6 and
preceding paragraph, the channel address diagnostic
clears flip-flop U40-9. This causes the Q output from
circuits produce duplicate channel address signals
U32-6 to inhibit AND gate U39-6 so that the read mode
during every other scan time (MEOS to MEOS). The
is enabled when the next end-of-scan signal occurs.
operation of the diagnostic channel address circuits is
Flip-flop U40-9 is held in the clear state to ensure that
identical to that of the functional channel address
flip-flop U32-8 is set for a high Q output by the next end-
circuits.
The major components in the diagnostic
of-scan signal and a normal read mode is produced.
channel
5-77
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