Diagnostic Circuits-CONT.

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

address circuits are active port multiplexer U1, U14,

frames eligible for overhead service is equal to the

active channel counter U6, R.A.M. U12, U13, read/write

number of used ports in the configuration.

port address selector U6, U23, and channel flip-flop set

U7. When a no-compare condition is detected by

5-303. When word 28 signal MW28 is applied through

address comparator U20, the output from OR gate U47-

inverter U45-6 to the port sequence error detector circuit,

12 goes high to initiate the write mode as previously

the Q output from flip-flop U38-5 goes high to enable one

described. The high output from OR gate U47-12 is also

input of AND gate U46-6. AND gate U46-6 remains

applied to flip-flop U30-7. The flip- flop, in turn, produces

inhibited to produce a high output during word 28 by the

sequencer diagnostic error signal MSEQ- when the

low inhibit input from inverter U45-6. In turn, the output

output from OR gate U47-12 is high and signal MRIO

from inverter U45-10 is a low input to flip-flop U38-9 until

occurs.

word 28 signal MW28 terminates at the end of word 28.

At the end of word 28, the output of inverter U45-6 goes

high and briefly enables AND gate U46-6 until system

5-301. End-of-scan activity detector U48-10 is held in

clock signal MRIO- occurs and the Q output of U38-5

conduction during normal operation by end-of-scan

goes low. While U46-6 is enabled, the output from U45-

signals MEOS2 from flip-flop U33-5. When the signals

10 is high to the K input of flip- flop U38. At the time that

are missing, the duty cycle of U48-10 expires and sets

signal MRIO- occurs, U38 is clocked and the Q output to

latch U39, U47 to produce loss of end of scan signal

AND gate U46-11 goes high. The Q output from U38-7

MLEOS-. The low output from U48-10 is also applied to

is driven high at the end of each word 28. Therefore,

OR gate U47-12 to initiate signal MSEQ- from flip-flop

when signal MMF=PS is generated during word 28, both

U30-7.

inputs to AND gate U46-11 are high for one clock time

and causes a high Q output from flip-flop U30-5 when

the next signal MRIO occurs. During the rest of word 28,

5-302. In normal operation, during each minor frame

the J and K inputs to flip-flop U30-5 remain low and the

period, port-is-in- sequence comparator U41 produces

Q output from the stage does not change. Therefore,

an A is greater than B (high) signal when the minor

the Q output from U30-5 is a high input to one input of

frame count in signals MMFCO through MMFC4 is

exclusive OR gate U28-11. When the minor frame count

greater than the count applied to U41 from the PORTS

applied to ports-in-sequence comparator U41 during the

IN USE switches. In each minor frame period that an A

minor frame period is equal to or less than the number of

is greater than B signal is generated, minor frame is in

used ports, a high input is applied from inverter U45-2 to

port sequence signal MMF=PS is not generated in a no-

the other input of exclusive OR gate U28-11. Therefore,

error condition. In turn, signal MMF=PS is generated

when word 28 is terminated, the output from inverter

during word 28 of each minor frame period that U41

U45-10 goes high for a brief time as explained above

does not generate the A is greater than B output signal in

and the high signal enables one input of AND gate U37-

a no-error condition.

This diagnostic function is

11. Since both inputs to exclusive OR gate U28-11 are

performed to ensure that a used port is not selected for

high at this time, a low inhibit signal is applied from U28-

overhead servicing during a minor frame period that is

11 to U37-11 to prevent the generation of error signal

not eligible for overhead service. The number of minor

PSERR-.

5-78