GATED CLOCK/DATA MUX (GC/DM) CARD.

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

5-304. When signal MMF=PS is generated during word

output stream that is routed to the reference timer card.

28 and an A is greater than B output is produced from

The block diagrams related to the block diagram

U41, an error condition exists. At this time, the input to

discussions are shown in figures 5-22 through 5-26. The

exclusive OR gate U28-11 from inverter U45-2 is low and

logic diagrams associated with the detailed circuit

the input to the exclusive OR gate from U30-5 is high.

discussion for the GC/DM card are in the circuit

This condition causes a high input to AND gate U37-11

diagrams manual.

from the exclusive OR gate at the time that a high is

applied to the other input of U37-11 from U45-10. This

5-308. BLOCK DIAGRAM DISCUSSION.

error condition allows AND gate U37-11 to be enabled

and produce error signal PSERR- to OR gate U47-12

5-309. Format Generation Function (Figure 5-22).

and produce the diagnostic signals previously described.

5-310. The generation of the timing signals is initiated

5-305. Self-test signal ST2- sets diagnostic latch U39,

and controlled by end-of-scan signals MEOS2B and

U47 and presets flip-flop U30-7 to generate diagnostic

MEOS2B- from the sequencer card. End- of-scan signal

error signals MSEQ- and MLEOS- during the self-test

MEOS2B- increments the word counter from words 1

mode. When the self-test mode is completed, error

through 29. Each time word 29 signal MW29 is

reset signal ERST clears flip-flop U30-7 and resets

generated, a preset-to-1 signal is applied to the counter

diagnostic latch U39, U47 to its normally off state when

from the words 28/29 decoder.

the equipment is in a no-error state. Signal ERST also

resets the circuits to their no-error state when the

5-311. The 5-bit word count signals WCO through WC4

DISPLAY RESET switch on the front panel is pressed.

from the word counter are applied to the word 27

decoder, the read only memory (ROM), and to the words

5-306. GATED CLOCK/DATA MUX (GC/DM) CARD.

1 through 23 decoder. The words 1 through 23 decoder

generates an enable signal to the ROM during word

5-307. GENERAL. The GC/DM card is one of the

times 1 through 23, and an inhibit signal to the ROM

common card types in the multiplexer set. One of the

during word times 24 through 29. The decoder also

GC/DM cards is used in the multiplexer and a second

generates word 24 through word 29 signal DW2429 that

card is used in the demultiplexer.

The functional

is applied to the data mux function on this card during

discussions for the circuits on the card are divided into

word times 24 through 29.

three parts: format generation functional circuits, which

generate word counts 1 through 29, minor frame counts

5-312. The ROM generates two sets of the three

1 through 31, terminal minor frame count 31, and the

stuffing codes NAC, NSC, PSC, and NACD, NSCD,

three overhead stuffing codes that are used in the other

PSCD during words 1 through 23. Signals NAC, NSC,

common cards; gated clock generation functional

and PSC are applied to the data mux function and

circuits, which generate the gated clock signals for up to

signals NACD, NSCD, and PSCD are applied to the

15 active channels; and data mux circuits, which perform

diagnostic data mux

time division multiplexing of the digital data from 1 to 15

function.

channel cards, plus overhead data, into one digital data

5-79