DETAILED CIRCUIT DISCUSSION. - TM-11-5805-688-14-10166

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

5-257. The card error detector circuit performs a

5-262. The data bits from U6-7 in the shift register are

diagnostic function. The detector samples outputs from

also applied through inverter U9-2 to the base circuits of

the bandpass filter and integrator circuits. When an error

transistor switches Q2 and Q3. When the output from

occurs, an error signal is generated from the detector

the inverter is low, switch Q2 is enabled and effectively

during word 24 on the positive stuff request (MPSTXX-)

grounds the negative input from slope control amplifier

line to the OEG card. Self-test signal ST1- generates an

U1-12 to the negative input (pin 1) of integrator U4-12.

error signal from the, circuit, during word 24, when the

The condition allows the positive drive voltage from

SELF TEST switch on the front panel is pressed. During

inverter U1-10 to drive U4-12. In turn, a high output from

word times other than word 24, signal MPSTXX- is not

U9-2 enables switch Q3 and effectively grounds the

used.

positive input from slope control amplifier U1-10 to the

negative input of integrator U4-12. In turn, this condition

allows the negative drive voltage from slope control U1-

5-258. DETAILED CIRCUIT DISCUSSION.

12 to be applied to integrator U4-12. Therefore, the

output from U4-12 varies in relationship to the polarity of

5-259. Functional Circuits.

the drive voltages applied to U4-1 from U1-12 or U1-10.

Figure 5-20 shows the variable output from buffer U4-10

5-260. The voice signals are applied to the primary of

as it is applied to comparator U3 to develop the error

isolation transformer T1. The input impedance of the

voltage that drives the encoder circuits.

transformer primary is 600 ohms. Operational amplifiers

U2-10 and U2-12 function as a bandpass filter circuit.

5-263. The Q and Q outputs from the three flip-flops

Operational amplifier U2-10 is configured as a low-pass

that make up the 3- bit shift register are routed to AND

filter circuit and operational amplifier U2-12 is configured

gates U8-6 and U8-12. When the three Q or Q outputs

as a high-pass filter circuit. The overall gain through U2-

are identical, the decoder logic generates a low-level

10 and U2-12 is approximately 6 db. The filtered analog

signal that biases Q1 off. This condition drives the

signals from U2-12 are applied to comparator U3. The

voltage level applied to pin 1 of U1-12 more positive and,

comparator also receives the reconstructed analog

in turn, drives the output from U1-12 more negative and

signals from buffer U4-10. 5-261. When the amplitude

the output from U1-10 more positive. The positive or

of the filter audio signal is greater than the amplitude of

negative driver voltage applied to pin 1 of integrator U4-

the applied reconfigured analog signal, a high-level (one)

12, in turn, causes the integrator output voltage to vary

output is generated from U3 to flip-flop U6-6 in the 3-bit

with an increased slope effect on the reconstructed

shift register. The output from comparator U3 is serially

analog signal applied to the comparator. As soon as the

clocked through the shift register by gated clock signals

decoder logic detects a reverse output from the first

MGCXX. Bit 1 from U6-6 is the pulse applied as a data

stage of the three-bit shift register, Q1 is biased back into

pulse to U5-6 in the data output buffer. The digital coded

conduction,

reducing

the

level

data bits are stored in the buffer for two multiplexer

system clock periods (MRIOX-) before being sampled by

the GC/DM card.

5-65