Wideband IF Signal Processing

TM 32-5865-069-24&P

being processed. The signals RCVR BLANKING and DELAY GATE 1-4 provide this infor-

mation. In the look-thru mode, the timing of FFT CNTRL REG CLK/DELAY also depends

upon the type of signal being processed. When not operating in the look-thru

mode, the timing of the signal is controlled by OBFA1 from the CPU.

3-3.8.4.1 Wideband IF Signal Processing. When a wideband IF signal is being

processed, the trailing ed e of RCVR BLANKING from line-receiver U5B triggers the

wideband IF delay circuit U14, U12A, U28B). This circuit provides a delay of

approximately 5 microseconds, compensating for the delay in the 200 kHz filter

used in the down converter. The output of the delay circuit is routed thru the

gating logic (U6A, U6B, U13A, U26B, U28C) to clock enable flip-flop U18A. U18A

transfers the state of OBFA1 to enable the FFT clock control logic circuit (U13C,

U13D, U21A, U21C, U24E) . The output of the gating circuit also triggers pulse

stretcher circuit (U1B, U7A). This circuit provides a pulse approximately 1 sec-

ond long. The leading edge is coincident with the delayed trailing edge of RCVR

BLANKING. At this time there is valid data in the signal input to AR1. The pulse

is output as the LOOK THRU MODE CONTROL signal and fed to the FFT clock control

logic. This signal, gated by TJ MODE, provides the FFT CNTRL REG CLK/DELAY

signal. FFT CNTRL REG CLK clocks control data onto the CDAT bus. DELAY clocks

status flag generator U15A to provide the CIVLD flag signal. CIVLD starts the

data processing cycle.

3-3.8.4.2 Video Signal Processing. Four signals, DELAY GATE 1-4, are buffered by

line receivers U8 and U9. These signals are fed to 4 to 1 multiplexer U1O. U1O

selects the appropriate receiver delay gate using control signals RCVR NO MSB,

RCVR NO LSB. The output of U1O is routed thru the gating logic circuit to clock

enable flip-flop U18A. U18A transfers the state of OBFA1 to enable the FFT clock

control logic circuit. The gate output also triggers pulse stretcher circuit.

This circuit provides a 1 second long pulse. The leading edge is coincident with

the leading edge of the selected receiver DELAY GATE. At this time there should

be valid data in the RCVR VIDEO signal input to AR1. LOOK THRU MODE CNTRL is

gated with TJ MODE in the FFT clock control circuit to provide the FFT CNTRL REC

CLK/DELAY signal. This signal is used to enable control data onto the CDAT bus

and set the CIVLD flag.

3-3.8.4.3 Bandwidth Check. The gating circuit also provides the signal RCVR BW

CHK . All the time there is valid data in the signal input to AR1, RCVR BW CHK

remains low. The function AIDSEL*, from the PAN processor, is used together with

PICCLK to fetch data samples from the ADAT register. These two signals and RCVR

BW CHK are fed into U14. When the PAN processor has collected the required number

of samples to provide a valid display, AIDSEL* is set high. When AIDSEL* goes

high, RCVR BW CHK is transferred to the output of U14 as the flag signal PDBWTN.

If RCVR BW CHK is high at this time, PDBWTN is set high. This indicates that

there is insufficient time to collect the required number of data samples to

provide a valid display. OBFA* resets the flag.

3-3.9 Carrier Presence Detector (CPD) CCA,(A1 - A4). Refer to FO-5, a functional

block diagram of a typical CPD. The RSPU contains four CPD. The CPD is an inte-

grating, peak responding, threshold detector. It is capable of detecting energy

levels at low signal to noise ratios with a typical response time of 2 milli-

seconds. An integrator disable circuit prevents the integrator bias from changing

in the presence of noise only. This allows the circuit to respond to low duty

cycle samples of CW, AM, FM, or SSB modulated signals. There are two versions of

the CPD. The differences are shown on FO-5.

3-20