Control Signals

TM 32-5865-069-24&P

c. Collects control data for the PAN data processor from the CPU.

Transfers processed data to the CPU.

3-3.8.1 CPU Interface. PPI device, U25, provides the interface between the CPU

(P/O A7) and the PAN processor. The interface allows the CPU to control the

operation of the processor and to collect processed data. The transfer of data

via U25 is controlled by the signals WR* and PPISEL2*. When these signals are

active, DATA BUS DO-D7 is transferred to the selected output port of U25. The

output port of U25 used for the transfer is determined by ADDR BUS AO-A1.

Processed data, DO-D7, is transferred via U25 to the CPU as DATA BUS D0-D7. This

occurs when the signals RD* and PPISEL2* are active. The transfer of data is

accompanied by handshake signals. U25 is reset by the CPU using SYSTEM RESET*,

inverted by U23B.

3-3.8.2 Control Signals. The FFT control register circuit is formed by U22A,

U22B, and U29. This circuit provides an eight-bit control word CDAT O-7. This is

used to control the PAN processor sequence. Four-bits of data from the PPI device

U25 provide the four MSB. The four LSB are zeros. CO*-C3* are used as test

inputs and normally pulled up high. Data is latched by FFT CONTROL REG CLK.

Decoder 1 (U34A) decodes two data-bits from U25 to provide three control signals:

WBIF*, NBIF*, and VIDEO*. Decoder 2 (U34B) decodes the two data-bits from U25

which represent the selected receiver number. VIDEO CONTL RCVR 1*-4* signals are

used to select one of four video signal inputs for processing. Decoder 2 outputs

are inverted to provide IF SEL RCVR 1-4. These signals are used to select the

appropriate IF signal for processing. Decoder 3 (U6C, U6D, U24A, U24B, U24C,

U28A) and inverter U24F provide the attenuation control signals 20DB1-3 and 10DB.

The mode signal TJ MODE is controlled by the CPU. OBFA* is a handshake from the

CPU to the PAN processor. This signal indicates that output buffer (port A) is

full. OBFA* is used to generate OBFA1 and 0BFA2 in inverter circuit U23E, U23F,

and U24D. IBFB is also a handshake from the CPU to the PAN processor. This

signal indicates the input buffer (port B) is full. IBFB is inverted by U23A and

used to generate the DODONE flag signal. ACKA* and ACKB* are handshake signals

from the PAN processor to the CPU. ACKA* informs the CPU that control data has

been received. ACKB* informs the CPU that processed signal data is ready for

collection.

3-3.8.3 Analog Data. The analog signal RCVR IF/VIDEO is fed to the input of

impedance matching amplifier AR1. The amplifier output RCVR ANALOG is fed to A/D

converter U19 and to the input over range detector circuit (U4, U18B). The refer-

ence amplifier circuit (U3A, Q1) provides the reference voltage for both U19 and

the detector circuit. When the amplitude of RCVR ANALOG exceeds preset limits,

the detector provides the flag signal PDSFIV. OBFA* is used to reset the circuit.

U19 converts RCVR ANALOG into an eight-bit digital word. Conversion is controlled

by PICCLK (the PAN processor clock signal). The data word is stored in the A data

processor to fetch the data (ADAT) from the A data bus.

3-3.8.4 FFT Control Register Clock. The signal FFT CNTRL REG CLK/DELAY is used

to enable control data onto the CDAT bus and to set the CIVLD flag. When this

occurs, the data processing cycle begins. When the AN/MLQ-34 system is in the TJ

and look-thru modes, FFT CNTRL REG CLK/DELAY is synchronized with the system

receive/transmit cycle. This is to ensure that there is valid data in the signal

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