Hz Tone Detector CCA, (A5)

TM 32-5865-069-24&P

3-3.9.1 Operation. The 21.4 MHz Narrowband IF (NBIF) signal from the receiver is

fed to the CPD. In the -2 version, NBIF is fed directly to the IF Amplifier (Q14,

Q15). In the -3 version, NBIF is first fed to S1. S1 is controlled by the logic

of 250 kHz SEL and 500 kHz SEL. When both signals are high, NBIF is fed thru FL1

to the IF Amplifier. FL1 rejects out of band noise. When either the 250 kHz or

500 kHz IF bandwidth is selected, S1 switches FL1 out. The output from the ampli-

fier is divided. One output is amplified by Q19 and fed out as NBIF 1 and 2. The

other output from the divider is amplified in two AGC controlled IF stages U2, Q1.

AGC is provided by peak detector (Q3, Q17, Q18) and filter circuit U3. This main-

tains a constant. peak level into the envelope detector Q2. LOOK THRU is used for

AGC optimization. The noise output from Q2 triggers first comparator U10 each

time it crosses the threshold offset level selected for a given IF bandwidth.

Offset levels are varied as a function of receiver IF bandwidth. This is con-

trolled thru FET switches U9, U21 to compensate for differences in noise charac-

teristics with different bandwidths. The output of the comparator is converted to

Vdc level by quantizer CR5 and CR6. When the output of U1O goes high, a posi-

tive reference voltage is applied to the input of the integrator (Q9, Q1O, U11,

U12) thru FET switch Q4. Simultaneously, the delay generator (Q12, U8, Q5) is

triggered. This closes Q4 allowing the integrator to charge toward the positive

reference voltage. When the noise signal voltage drops below the threshold offset

level at the U10 input, the output of U1O switches the negative reference voltage

to the integrator thru Q4. This causes the integrator to discharge toward the

negative voltage reference until Q4 opens. The delay time constant is chosen such

that the integrator discharges after each threshold crossing for a length of time

equal to the average noise pulse width characteristic of the selected IF band-

width. The delay time constant is varied as a function of receiver IF bandwidth.

This is controlled thru FET switches U7 and U20. The output of the integrator is

constantly compared against a DC voltage from the Signal Noise Ratio (SNR) set

control Q7 and Q8, by a second comparator U13. The output of the comparator is

fed to a latch U14B (a one bit shift register). The clock for the shift register

comes from the counter circuit (U6, U7, U18A). The dump control circuit (U14A,

U18B) generates the DUMP command. Dump is used to discharge the integrator. The

timing of DUMP is controlled by the external 250 kHz clock applied to the coun-

ters. INTEGRATOR DUMP resets the counters resulting in an internal sample pulse

at the appropriate sample time. When SAMPLE GATE occurs, a zero voltage is

applied to the integrator and the counters are halted. The outputs from U14B are

transferred to the output via a differential line driver as CPD, and from the buf-

fer circuit as CPD LOCAL. The INT DONE is provided as an output to external

units.

3-3.10 150 Hz Tone Detector CCA, (A5). There are four identical channels of tone

detection on A5. Refer to figure 3-12, a functional block diagram of a typical

channel (RCVR No. 1 is shown and discussed). The purpose of the tone detector is

to detect a 150 Hz signal in the presence of noise and other modulation. This

must be done with a low probability of false alarm and a high probability of de-

tection. The main device for this operation is a 150 Hz detector micro-circuit

U9). In addition to the detector, there are three operational amplifiers

AR1-AR3) and line driver (U2, Ul). The input to the detector is AUDIO with band-

width of 30 Hz to 250 kHz. It is amplified in AR1 and routed to U9 thru a 2:1

attenuator. The output from U9 is driven out as TONE DET RCVR 1 and TONE STAT

RCVR 1. The audio from AR1 is attenuated and buffered by AR2 and AR3. AR2 pro-

vides AUX AUDIO OUT RCVR #l and AR3 VIDEO RCVR #1.

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