Description of Logic

TM 11-6625-922-15

the stable 2 MHz oscillator (A4) output (2). Signal No.

(1) A 2-MHz signal derived from a precise

2 is divided in the countdown logic assembly (A10) and

crystal-controlled oscillator is divided by 10 (M2/A10),

passed (8) to delay logic assembly (A9) where it is

then divided by 5 to provide a 40-kHz signal (M3/A10).

further divided to produce a square wave at the proper

This signal is divided by 3 (M4/ A10, M5/A10) and also

frequency (9). This square wave (9) is passed through

divided by 10 (M6/A10), producing three signals,

an active low pass filter assembly (A13) where it is

selectable by the MODULATION FREQUENCY HZ

filtered to a sine wave (10). Signal No. 10 is then

switch (SIB) to provide the modulating frequencies of

passed to the modulating signal inputs of assemblies

250, 83-1/3, and 25 Hz; then the signal at SIB is divided

A14 and A15.

by 2 (M1/A9), divided by 5 (M2, 3, 4/A9), divided by 4

(M5, 6/A9), and then divided by 4 (M7, 8/A9). The last

c. Delay Reference Signal Generation. The delay

three dividers provide a total division of 80, for deriving

reference signal used to make the phase comparison in

the time segments. A double level AND gating system,

delay output assembly (A8) is generated from the stable

consisting of gates CR1, CR2, CR3 (T1) through CR25,

2-MHz signal (2) from A4. This signal is divided in A10

CR26 (T13) on assembly A9, is used to decode and

and A9 to provide a chain of pulses (11) to the coarse

select 1 out of 80. The decoding matrix progress is from

and fine delay switches (12). The signals at No. 12 are

80 to 13 to 3 to 1. The input signal to the divide-by-80

further gated in A8. This sequence is explained in detail

(M1/A10 pin 6) is used as a final Strobe signal to

in paragraph 5-5.

eliminate any ambiguity in decoding. The time pulse

d. Receiving Circuits. The signal at the receive

thus generated at AND gate CR3, CR4, CR5 and CR6

input is amplified and demodulated in A6 and the

on assembly A8 is used to set flip-flop M1/A8. The

demodulated signal (13) is passed through A7 where all

demodulated input signal from ST/A8 is then used to

the carrier components are filtered out to leave only the

reset flip-flop M1/A8. The one output (Q) of the flip-flop

modulating signal (14) which has been delayed by the

is low-pass filtered to recover the average direct-current

amount of carrier frequency delay in the transmission

(dc) level, which corresponds to the duty cycle, or time

line.

between set and reset signals. The DELAY meter

e. Frequency Sweeping. The variable frequency

indication is proportional to the dc voltage.

oscillation (A2) can be electronically swept over its

(2) A

constant

offset

equivalent

frequency range by a triangular waveform (15)

approximately 25 percent of a time period is used in

generated in the sweep drive assembly (A16). This

both the digital and the analog circuitry. When the

electronic sweeping capability substitutes for the manual

coarse range is being used, the flip-flop output pulse

front panel carrier frequency control.

should be between 25 and 50 percent of the time.

f. Analog Outputs. Each meter and the digital

When in the fine range, the output should be between

display provide dc output signals proportional to their

25 and 26.5 percent, to prevent wild voltage changes

readings. These output signals are brought out to the

near zero on the DELAY meter. Without an offset, an

rear panel terminal strip. The analog frequency signal is

output pulse with a 2 percent variation around 0 percent

generated in A3 from input signal No. 16. The analog

would produce duty cycle extremes of 1 and 99 percent

delay signal is generated in A3 from signal No. 17. The

instead of 24 to 26 percent with the present system.

analog level signal is generated in A12 from signal No.

The DELAY meter cannot accept the abrupt voltage

18.

changes.

5-5. Description of Logic

b. Logic For Frequency Measurement (fig. 5-4 and

(fig. 5-4)

5-5)

a. Logic for Delay Measurement. The time period

(1) Timing for frequency measurement is

of the modulation signal is divided into 80 equal time

derived from the same 2-MHz oscillator used for delay

segments by logic circuitry within the TS-2669/GCM.

measurement. The 4-kHz signal (M6/A10 pin 12) is

These 80 time segments are selected by the COARSE

divided by 40 to derive a 100-Hz signal (M10/A10), then

DELAY MS switch (four-position) and the FINE DELAY

divided by three groups of 10 (fig. 5-5) (M11/A10,

MS switch (20-position). The full scale of the DELAY

M12/A10, M13/A10 to provide 10, 1, and 0.1-Hz signals

meter can then be used to indicate 1/80th of a time

for the sampling time interval to count input pulses.

period. This method is used to determine the phase (or

COUNTING TIME switch (S7) selects one of

time) relationship of two signals of the same frequency,

which correspond to a measurement of envelope delay.

5-3