DETAILED SELF-TEST CIRCUIT DISCUSSION

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

These inhibit conditions effectively disable all the

OR gate are low in a no-error condition and the OR gate

multiplexer diagnostic error signals applied to the display

output is still low. Therefore, the OR gate produces a

card.

low-level output in the operating mode and also in the

self-test mode in a no-error state. Therefore, the

c. Setting switch S1 to the DEMUX OFF position

operation of the functional circuits that process the

applies an inhibit (ground) to AND gates U16-8 and U16-

signals applied through the OR gates is the same in the

11 to inhibit the DLOT and DTMOG inputs to the display

self-test mode as described previously. Also, in the self-

card. The inhibit produces a high output from OR gate

test mode, all the out-of tolerance signals applied to the

U36-8 that is applied to inverter U15-8. Inverter U158, in

display card become high in a no-error condition.,

turn, produces a low inhibit signal to flip-flop U17-10 and

a master reset to counter U9 in the demultiplexer

5-606 n the normal operating mode, multiplexer and

channel card error detector. The low inhibit signal from

demultiplexer shift registers U39 and U44 in the self-test

switch S1 is also applied through inverter U14-6 to inhibit

delay enable circuit are held in a reset condition by the

demultiplexer common card error priority encoder U31.

self-test low ST2- signal from inverter U45-4. Since the

These inhibit conditions effectively disable all the

two shift registers are operationally alike, only the

demultiplexer diagnostic error signals applied to the

operation of U39 in the multiplexer function is discussed

display card.

in paragraph 5-607.

5-607. Before a self-test function is initiated, the low Q1

5-604. DETAILED

SELF-TEST

CIRCUIT

output from shift register U39 is applied to exclusive OR

DISCUSSION.

gate U40-6. The output from U40-6, is a high-level input

to OR gate U36-12. When the multiplexer diagnostic

5-605. Setting the SELF TEST switch on the front panel

circuits are operational, all inputs to U36-12 are high to

to the on (up) position applies self-test signal ST2- to the

produce a low-level output. The low-level output is

display card. This results in a change in the signal level

applied through inverter U15-10, producing a high-level

applied to one input of each exclusive OR gate in series

signal to the clear input to flip-flop U17-6 and to the

with each diagnostic error signal input to the card. In

master reset on counter U8 in the multiplexer channel

turn, the diagnostic error signals that are normally high in

card error detector circuit. At the time that a self-test

a no-error state are inverted to become low input signals

function is initiated, self-test signal ST2- goes low and

in the no-error state during the self-test mode.

results in a high input to one input of OR gate U40-6. In

Therefore, this switch to both inputs to each exclusive

turn, the output from U40-6 goes low (output from Q1 on

OR gate results in no change in the output from each OR

U39 to U40-6 is still low) and produces a high output

gate, since both inputs to the OR gate retain the same

from OR gate U36-12. The high-level signal applied

relationship to each other. For example, in normal

from U36-12 through inverter U15-10 produces a low-

operation, exclusive OR gate U42-8 receives a high level

level clear input to flip-flop U17-6 and a low-level master

loss-of-timing signal MLOT input and a high-level self-

reset to counter U8.

test signal ST2 input and the OR gates produces a low

output. In the self-test mode, both input signals to the

5-164