DETAILED FUNCTIONAL CIRCUIT DISCUSSION-CONT.

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

Each time U10 clocks U26, the low-level output from

card address encoder. This state produces all low inputs

AND gate U19-6 inhibits AND gate U11-6 in the input

to binary-to-BCD converter U12 and inhibits a card

circuit of one-shot multivibrator U1. The inhibit signal to

address from being generated from U12 when a loss of

U11 prevents U1 from being triggered on by a transition

timing occurs.

pulse at the time counter U26 is being clocked. When

U1 is triggered on, the low-level output signal from U1 is

also applied as an out-of-tolerance error signal to system

5-602. Lamp test signal LT is applied from the front

priority encoder U7.

An out-of-tolerance signal is

panel to inverter U35-2 when the LAMP TEST switch on

processed through U7 and the card address encoder in

the front panel is pressed. This condition forces the

the basic sequence as previously described.

decoder logic to generate the six enable signals to light

all the indicators on the front panel.

5-599. Demultiplexer loss of timing signal DLOT- is

applied through exclusive OR gate U38-8 and AND gate

U16-11 to an input on system priority encoder U7.

5-603. Switch S1 on the display card is set to one of

Demultiplexer OEG card diagnostic signal DTMOG- is

three positions. In the NORM position, the multiplexer

applied through exclusive OR gate U42-11 and AND

and demultiplexer diagnostic circuits are enabled. In the

gate U16-8 to an input on U7.When either error signal is

MUX OFF position, only the demultiplexer diagnostic

in an error state, the error signal is processed through

circuits are enabled. In the DEMUX OFF position, only

U7 in the basic sequence previously described. Signal

the multiplexer diagnostic circuits are enabled. The

DLOT- is also applied, from AND gate U16-11, as loss-

diagnostic logic applications that enable or disable the

of-timing remote alarm signal DLOTRA- to the

diagnostic circuits are described in the following

sequencer card to report a demultiplexer loss-of-timing

subparagraphs.

condition.

a. In the NORM position, the application of +5 volts

5-600. Reference timer diagnostic signal MRT- is

enables the diagnostic circuits described in detail in

applied through exclusive OR gate U40-8 and AND gate

subparagraphs b and c.

U16-3 to an error input on system priority encoder U7.

When the signal is in an error state, the error input is

b. Setting switch S1 to the MUX OFF position

processed through U7 in the basic sequence previously

applies an inhibit (ground) to AND gate U16-6 to inhibit

described.

the MLOT- input to the circuits. The inhibit from S1 also

produces a high output from OR gate U36-12 that is

5-601. Multiplexer loss-of-timing signal MLOT- has the

applied to inverter U15-10.Inverter U15-10, in turn,

highest priority of all the error signals applied to system

produces a low inhibit signal to flip-flop U17-6 and a

priority encoder U7. Signal MLOT- is applied through

master reset (clear) to counter U8 in the multiplexer

exclusive OR gate U42-8, AND gate U16-6, and inverter

channel card error detector. The low inhibit signal from

U15-4 to error input El on U7. In an error state, the high

switch S1 is also applied through inverter U15-6 to inhibit

signal applied to E1 on U7 forces the GS output from U7

multiplexer common card error priority encoder U33.

high. Signal MLOT- is the only error input to U7 that

The low inhibit input to AND gate U11-6 in the out-of-

forces the GS output high. A high from the GS output is

tolerance circuits disables the out-of-tolerance signals

applied through inverters U15-12 and U15-2 to produce a

from out-of-tolerance multiplexer U34.

high inhibit signal to multiplexers U2 through U6 in the

5-163