DETAILED SELF-TEST CIRCUIT DISCUSSION-CONT.

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

Signal ST2- applied to OR gate U40-11 in the

be generated from AND gate U32-8 when all the

demultiplexer circuits results in an inhibit signal

multiplexer diagnostic error inputs to the display card are

processed through OR gate U36-8 and inverter U15-8 to

in a no-error state. At this time, the outputs from AND

clear flip-flop U17-10 and master reset counter U9 in the

gates U47-6 and U47-8 are high inputs to AND gate

demultiplexer channel card error detector circuit.

U32-8.

Also, the output from inverter U27-6 that

monitors the out-of-tolerance circuits is a high input to

5-608. In the self-test mode, the initial low Q1 output

AND gate U32-8. In turn, the low-level output from U32-

from shift register U39 applied to exclusive OR gate U40-

8 is applied through OR gate U23-6 to place a high-level

6 inhibits the multiplexer card diagnostic error function as

(no error) input to AND gate U22-8. The same basic

described in paragraph 5-607. When self-test signal

sequence is performed by diagnostic AND gates U25-8,

ST2is applied to the display card, the low-level inhibit

U46-6, U46-8, and U32-12 and OR gate U23-3 to place

signal to the master reset input is removed and counter

a high input to pin 12 on AND gate U22-8, representing a

U39 is enabled. At this time, the Q1 output from U39 is

no-error condition of the demultiplexer circuits. The third

still low. The shift register is initially clocked when minor

input to pin 9 on AND gate U22-8 is signal ST2-, which is

frame signal MMF31A is applied to a data input on U39

high in the self-test mode. The remaining input to pin 13

and word 24 end of scan signal M24EOS2 is applied to

on AND gate U22-8 is applied from OR gate U13-8.

the clock input of U39. A high is clocked out of Q1 on

When a no-error state exists in the secondary diagnostic

U39 when the next (second) M24EOS2 signal is applied

circuits, the output from OR gate U13-8 is a low inhibit

to the shift register. At this time, the output from

signal to AND gate U22-8, which then produces a high

exclusive OR gate U40-6 goes high and removes the

output. The operation of OR gate U13-8 is described in

clear signal from flip-flop U17-6 and the master reset

paragraph 5-610. When an error is detected in the

from counter U8. A high is clocked out of Q2 on U39

secondary diagnostic circuits, the output from OR gate

when the next (third) M24EOS2 signal is applied to the

U13-8 goes high and enables AND gate U22-8. The low

shift register. The Q2 signal is applied through inverter

inhibit signal from U22 is applied to one input of AND

U35-8 and OR gate U30-6 to enable one input of AND

gate U36-6 to force its output high. The high output from

gate U36-6. At approximately the same time, the output

AND gate U36-6 is applied through OR gate U30-3 to

from OR gate U30-8 in the demultiplexer function

place a high input on exclusive OR gate U46-3.

enables another input of U36-6.The third input to AND

Exclusive OR gate U46-3, in turn, produces multiplexer

gate U36-6 from AND gate U22-8 should be high (no-

card error signal LMCRD that causes the

error state) so that a low output signal from U36-6 is

MULTIPLEXER CARD indicator on the front panel to go

produced. The low signal from U36-6 to inverter U27-8

out. The low output from U22-8 is also applied through

and OR gate U30-3 enables the operation of the lamp

inverter U35-12 to drive the outputs from inverters U21-

display decoder logic circuits for decoding error

4, U21-6, and U21-2 low. At the same time, the output

conditions detected in the self-test mode.

from inverter U35-12 is also applied to the E input on

binary-to-BCD converter U12 to drive all the outputs

5-609. In the multiplexer secondary diagnostic check,

high. The result is a count 22 (UA1 and TA1 are high) to

the functional AND operation causes a low-level signal to

the digital display circuits on the front panel.

5-165