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T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3010
An SB card that has a minimum of used ports assigned
one of five values (153.6, 76.8, 50, 38.4, or 19.2 kHz);
to  it  may  not  obtain  the  required  bit  counts
and the smoothing function performed by the APLL
(approximately eight) to establish a compare in the
circuit in the NBSB card provides for a more gradual
address comparator before the next one or more
slewing of the output data bit rate than occurs in the SB
DW240X signals are applied.
card. The NBSB card APLL circuit compensates for a 1-
bit adjustment (caused by positive or negative stuffing) of
5-418. At the time that the read 4-bit address applied to
the input gated clock rate by gradually shifting the card's
address comparator U24 is the same address as that
output rate one bit over an interval of approximately 20,
stored in write address latch U19, an A=B signal is
000 data bit times. This same smoothing function on the
applied from U24 to flip-flop U36-10.  The next read
SB card is performed over an interval of approximately
clock signal produces a high signal from U36-10 that is
1,000 bit times.
applied to AND gate U15-11. At the time that the write
address latch was set, the data bit associated with the
5-422. DETAILED CIRCUIT DISCUSSION.
stored write address was clocked into flip-flop U36-6 by
the output from AND gate U15-3. Therefore, the data
5-423.  The following discussion describes the APLL
output from data buffer U1-5 should be the same data
circuit as shown in the NBSB card logic diagram in the
pulse that is stored in U36-6. When the two pulses are
circuit diagrams manual. Except for the APLL circuit, the
identical, the output from exclusive OR gate Ull-3 is low
reference designations for all the other circuits on the
and the output of flip-flop U3-10 remains high. When the
NBSB card and the SB card are the same as shown in
data bits being compared are not identical, the output of
their respective logic diagrams. In the APLL circuit, the
exclusive OR gate Ull-3 goes high and enables AND
count 8 output from write address counter U18 is
gate U15-11. The low output from U15-11 is clocked
inverted through inverter U10-8 and is applied as the
through flip-flop U3-10 as a low signal to OR gate U14-8.
reference input to pin 3 of phase detector U25.  The
The high output from U14-8 enables AND gate U15-6,
count 8 output from read address counter U21 is applied
causing OR gate U7-6 to generate card error signal
directly to pin 14 of phase detector U25 as the variable
DPSTXX through inverter U10-12.
input.  Even though the write address count output is
used as the reference input to U25, it will be seen that it
5-419.
NARROW BAND SMOOTHING BUFFER
is the overhead function of adding or deleting gated clock
pulses at the input to U25 that causes the phase detector
(NBSB) CARD.
function to detect a phase shift. This application causes
the phase detector to initiate commands that force the
5-420. GENERAL.
read address to follow the pulse changes from the write
address counter.  Phase detector U25 monitors the
5-421. The operation of the NBSB card is basically the
positive-going transition of each of the two pulses applied
same as that of the SB card described in paragraphs 5-
to it. When the two count 8 outputs are proper, there is a
396 through 5-418.  The only difference between the
difference count of eight between the two 4-bit
NBSB card and the SB card is in the electrical
addresses. Therefore, the count 8 pulse from the write
configuration of the APLL circuit as described in
address counter is high when the count 8 pulse from the
Functionally, the
read address counter is low. Since the count 8 from the
overall operation of the two cards is the same, with two
write address counter is applied through inverter U10-8
exceptions: the output rate of the NBSB card is limited to
to U25,  both pulses applied to U25 have the same
phase and polarity in normal operation.
5-112

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