Click here to make tpub.com your Home Page

Page Title: Diagnostic Circuits
Back | Up | Next

Click here for thousands of PDF manuals

Google


Web
www.tpub.com

Home


   
Information Categories
.... Administration
Advancement
Aerographer
Automotive
Aviation
Construction
Diving
Draftsman
Engineering
Electronics
Food and Cooking
Logistics
Math
Medical
Music
Nuclear Fundamentals
Photography
Religion
   
   

 

T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3010
causes emitter followers Q5 through Q8 to produce a
The functional operation of these circuits is the same as
higher or lower (unbalanced) dc voltage to the base
that described for the coarse rate conversion circuits in
circuits of Q9 and Q11. When one of the two stages is
the RCB card. The specific components associated with
forced into conduction, Q10 turns off and produces a
the functions performed in the CRC circuits are shown
high output that is applied to inverter U10-4 in the
on the block diagram in figure 5-32.
composite diagnostic logic.  The output from inverter
U10-4, in turn, causes error signal DPSTXX to be
5-415. Diagnostic Circuits. In a no error condition, the
generated. In the timing output drivers circuit, Q19, Q21,
three error inputs to OR gate U14-8 are high to produce
and Q20 perform the same diagnostic function for the
a low input to AND gate U15-6. The high output from
timing output drivers circuit. The output from Q20 is
U15-6 enables the strobe input to OR gate U7-6. This
applied to inverter U10-2 in the composite diagnostic
condition produces a low output from U7-6 since all
logic, resulting in generation of error signal DPSTXX-.
inputs to U7-6 are high in a no error condition. When
one of three error inputs to OR gate U14-8 goes low, the
5-417.
A diagnostic address compare function is
output from AND gate U15-6 goes high and produces a
initiated when word 24 bit 0 signal DW240X is applied to
low inhibit strobe input to OR gate U7-6. This condition
the SB card. Signal DW24OXis applied through inverter
forces a high from U7-6 that produces card error signal
U34-10 to enable AND gate U15-3. The other input to
DPSTXX through inverter U10-12. When an error signal
AND gate U15-3 is enabled when the last diagnostic
is generated by one of the outputs from the drivers circuit
address compare function is completed. If the previous
and is applied through inverter U10-2 or U10-4, latch
diagnostic address compare function is not complete at
U14, U15 is set and holds the diagnostic circuits in the
the time signal DW240Xis applied, a new address
error state until the DISPLAY RESET switch on the front
compare is not initiated.  When AND gate U15-3 is
panel is pressed. At this time, reset signal DERRS is
enabled, the output signal is applied through inverter
applied through exclusive OR gate U11-11 to reset latch
U16-6 to clock the preset 4-bit write address into write
U14, U15 and returns the diagnostic circuits to their no-
address latch U19. The low output from AND gate U15-
error state, assuming that there are no faulty circuits on
3 is also used to set latch U29-6, U29-8.  The latch
the card. In the self-test mode, signal ST1is applied to
output, in turn, applies a high input that is clocked into
exclusive OR gate U11-8 to produce a low inhibit signal
the J input of flip-flop U30-10 by the next read clock from
to AND gate U15-6. The output from U15-6 at this time is
the APLL circuit. At this time, the Q output from U30-9
an enable strobe to OR gate U7-6. At this time, OR gate
presets flip-flop U30-7 and resets latch U29-6, U29-8.
U7-6 only produces the desired error condition when all
The output from flip-flop U30-7 enables address
three error inputs applied to it are low. When all three
comparator U24 and presets flip-flop U37-9 whose
error inputs are low, the output of U7-6 goes high,
output inhibits AND gate U15-3.  The inhibit signal to
causing signal DPSTXX to be generated. When the self-
U15-3 prevents the next DW240Xsignal from entering a
test function is complete, signal ST1goes high and error
new 4-bit address in U24 before the existing compare
reset signal DERRS is applied to the circuits to reset
function is completed.
them to their no-error state.
5-416. A faulty condition in the data output drivers circuit
5-111

Privacy Statement - Press Release - Copyright Information. - Contact Us

Integrated Publishing, Inc. - A (SDVOSB) Service Disabled Veteran Owned Small Business