Coarse Rate Conversion Circuits

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

Therefore, a series of less positive (+0.75V) dc control

U26 and is then applied to divide-by-2n counter U32. In

signals is generated from the output of phase detector

switch position A or C, U26 is bypassed and the output

U20. In turn, the signals are applied to the active filter

from U31 is applied directly to U32. The selected output

circuit.

from U32 has several functions. One output is routed

through inverters U33 and U2-8 as the read clock signals

5-411. The active filter circuit contains a series of

that increment read address counter U21. One output

programmable RC time constant that are associated with

from inverter U33 and U2-10 is applied as the output

operational amplifier U25. A series of more positive

clock signals to clock the data bits (DATOUT and

signals from U20 is processed into a negative-going dc

DATOUT-) through output buffer U1 to the data output

slope voltage that is applied as a control voltage to

drivers circuit. The output clock signals are also applied

voltage-controlled multivibrator (VCM) U31. In turn, a

through three inverters U2 to produce timing output

series of less positive signals from U20 is processed into

signals TIMOUT and TIMOUT to the timing output

a positive-going dc slope voltage that is applied to U31.

drivers circuit. The output applied through inverter U2-10

There are two VCM's in U31. The positions of switches

is applied as output clock signals that clock diagnostic

S24 and S25 determine which VCM is used in a given

flip-flop U36-9. In the overall APLL operation, the

system application. A positive-going dc slope voltage

deletion of an incoming gated clock pulse causes U20 to

causes the output frequency from U31 to increase. A

detect that the pulse transition from the read address

negative-going dc slope voltage causes the output

counter is leading the pulse transition from the write

frequency from U31 to decrease. The output from U31

address counter. The result is that the read clock pulses

is applied through switch S25 to divide-by-16 counter

from the APLL circuit to the read address counter start to

U26 or to divide-by-2 counter U32.

decrease in frequency very slowly, hardly affecting the

overall nominal bit rate. In turn, the addition of a gated

5-412. Six switches are involved in the configuration of

clock pulse causes U20 to detect that the pulse transition

the APLL circuit. Each switch has four positions (A

from the read address counter is lagging the pulse

through D). The switches are as follows: S7 in the input

transition from the write address counter. The result is

circuit of integrator U25; S12 that selects the time

that the read clock pulses from the APLL circuit to the

constant associated with U25; S24 and S25 that select

read address counter start to increase in frequency very

one of the two VCM's (U31) to be activated; S8 that adds

slowly. The functional waveform representation of the

or removes divide-by-16 counter U26 from the

APLL circuit function is shown in figure 5-31.

configuration; and S5 that selects the one output

frequency from the APLL circuit that equals Fo for the

5-414. Coarse Rate Conversion Circuits. When switch

channel. The frequencies associated with each of the

S3 is in the SB position, a +5-volt enable signal is applied

four switch positions A through D are shown opposite

to one input of AND gate U16-3. This configuration

switch S5 on sheet 3 of the SB card logic diagrams.

allows each gated clock signal DGCXX applied to the SB

card to be routed to the write address counter. When

5-413. Divide-by-16 counter U26 is activated when

switch S3 is in the URD position, a selected number of

switch position B or D is selected for a given circuit

incoming gated clock pulses is inhibited by inhibit signals

configuration. The output from U31 is divided by 16 in

applied from the CRC circuits to AND gate U16-3.

Change 1 5-110