APLL Circuit - TM-11-5805-688-14-10210

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

The 4 bit read addresses that select the locations from

which the data are read out are produced by read

5-410. APLL Circuit. The count 8 output from write

address counter U21. Read address counter U21 is

address counter U18 is inverted and applied as the

incremented by the read clock pulses from the APLL

reference input to pin 1 of phase detector U20. The

circuit. The data pulses from the storage register are

count 8 output from read address counter U21 is applied

serially clocked through data output buffer U1-5 as

directly to pin 3 of phase detector U20 as the variable

complementary outputs DATOUT and DATOUT-

input. Even though the write address count output is

used as the reference input to U20, it will be seen that it

5-409. Data pulses DATOUT and DATOUT are applied

is the overhead function of adding or deleting gated clock

through polarity switch S10 to amplifiers Q2 and Q3 in

pulses at this input to U20 that causes the phase

the data output drivers circuit. Switch S10 provides a

detector function to detect a phase shift. This application

way to change the phase relationship of the two data

causes the phase detector to initiate commands that

pulse outputs with respect to the associated timing

force the read address to follow the pulse changes from

pulses to meet different system configuration

the write address counter. Phase detector U20 monitors

requirements. Transistor is a constant-current source

the negative going transition of each of the two pulses

for amplifiers Q2 and Q3. Amplifiers Q2 and Q3, in turn,

applied to it. When the two count 8 outputs are proper,

drive push-pull emitter followers Q5 through Q8. Setting

there is a difference count of 8 between the two 4-bit

switches S14 and S15 to the balanced (B) position

addresses. Therefore, the count 8 pulse from the write

connects breakdown diodes VR2 and VR3 (3.3 vdc) in

address counter is high when the count 8 pulse from the

parallel with breakdown diodes VR1 and VR4 (6.2 vdc).

read address counter is low. Since the count 8 from the

The breakdown diodes are in the base circuits of the

write address counter is applied through an inverter to

push-pull emitter followers.

In the balanced

U20, both pulses applied to U20 have the same phase

configuration, +3-volt channel data out signals DOXX

and polarity in normal operation. When the two

and DOXX are produced.

In the unbalanced

transitions of the pulses occur at the same time, U20

configuration, switches S14 and S15 are set to the U

determines that they are phase locked and the output

position to remove breakdown diodes VR2 and VR3 from

from U20 returns to a +1.5 volt level. When a gated

the circuits and let breakdown diodes VR1 and VR4

clock pulse to the write address counter is deleted, U20

control the base voltages to the push-pull emitter-

detects that the pulse from the read address counter is

followers. In the unbalanced mode of operation, a +6-

leading in phase the pulse output from the write address

volt signal DOXX is produced. In the unbalanced mode

counter. Therefore, more positive (+2.25V) dc control

of operation, switch S18 grounds the DOXX output.

signals are generated from U20 and are applied to the

Switch S19 provides the appropriate wave-shaping

active filter circuit. The dc control signals are generated

capacitor associated with the three different output

until a phase lock is obtained between the two pulses

conditions: balanced mode of operation or a 75-ohm or

applied to U20. In turn, when an additional gated clock

6K-ohm unbalanced mode of operation. Operation of the

pulse is generated, U20 detects that the pulse from the

timing output drivers circuit and associated switches is

read address counter is lagging the pulse from the write

functionally the same as that of the data output drivers

address counter.

circuit and associated switches discussed previously.

Change 1 5-109