Click here to make tpub.com your Home Page

Page Title: DETAILED CIRCUIT DISCUSSION
Back | Up | Next

Click here for thousands of PDF manuals

Google


Web
www.tpub.com

Home


   
Information Categories
.... Administration
Advancement
Aerographer
Automotive
Aviation
Construction
Diving
Draftsman
Engineering
Electronics
Food and Cooking
Logistics
Math
Medical
Music
Nuclear Fundamentals
Photography
Religion
   
   

 

T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3011
The end-of-scan signal DEOS3NX, together with word
is applied to the diagnostic flip-flop.  When the next
24 DW24NX-,  clocks a data bit into the 5-bit shift
output clock signal from the divide-by-2n counter is
register so that an inhibit signal is clocked out from the
applied to the flip-flop, a compare enable signal is
register during word 29. The inhibit signal during word
generated by the flip-flop.  At this time, the compare
29 inhibits the word counter and the gated clock control
enable is applied to the data compare logic to perform a
so that a gated clock is not deleted during word 29.
compare of the data bit stored in the data latch against
Each word Count from the word counter is applied as the
the equivalent data bit out of the data output buffer.
A input to the 10-bit comparator. Before the circuits are
Since the two bits have the same address, they should
activated, 10 fill-bit strapping switches (0 through 9) are
be identical pulses. When they are not the same, an
strapped to a predetermined count that is related to the
error signal is developed and applied to the composite
number of gated clocks to be deleted during a major
diagnostic logic to generate a card error output signal.
frame.  The 10-bit binary code from the strapping
The card error output signal is applied on the positive
switches is applied as the B input to the 10-bit
stuff request (DPSTXX-) line to the OEG card.
comparator.
The  10-bit  comparator  continually
compares the 10-bit binary code (A) from the word
5-406.  The composite diagnostic logic also receives
counter against the programmed 10-bit binary code
error inputs from the data output drivers and the timing
applied from the fill-bit strapping switches. Each time a
output drivers circuits. When any one of the three error
binary code applied as the A inputs is less than the
signals is applied to the logic, the card error signal
programmed B input, the gated clock inhibit signal is
(DPSTXX-) is generated.  The composite diagnostic
generated and applied to the gated clock control logic.
logic is reset by error reset signal DERRS when the
The outputs from the word counter are reversed so that
DISPLAY RESET switch on the front panel is pressed.
the MSB of the counter is applied to the LSB of the A
In turn, the composite diagnostic circuits are enabled and
input to the 10-bit comparator.  As a result, the near
produce signal DPSTXX when self-test signal ST1is
homogeneous spread of the gated clock deletions is
applied when the SELF TEST switch on the front panel is
obtained by the reversed binary count function.
set to the on (up) position.
5-405. Diagnostic Circuits. A data diagnostic compare
5-407. DETAILED CIRCUIT DISCUSSION.
function is initiated when word 24 bit 0 signal DW240X is
applied to the address compare control circuit (Figure
5-408.  Input-Output Buffer Function. The incoming
FO-4).  At this time, the address compare control
channel data pulses (DTIX-) are clocked through data
generates an enable signal to the write address latch and
input buffer U1-8 and are applied serially to data elastic
to the data latch. The write address latch stores the 4bit
storage register U22, U23. The data are clocked through
write address associated with the data bit that is being
the buffer and into the storage register by gated clock
written into the data latch and the data elastic storage
signals DGCXX.  The gated clocks increment write
register at this time. Approximately eight bit times later,
address counter U18, which, in turn, produces the
the address comparator receives a 4-bit read address
sequential 4-bit write addresses that are applied to the
that should compare with the address stored in the write
data elastic storage register.
address latch. The A=B signal generated by a compare
5-108

Privacy Statement - Press Release - Copyright Information. - Contact Us

Integrated Publishing, Inc. - A (SDVOSB) Service Disabled Veteran Owned Small Business