BLOCK DIAGRAM DISCUSSION - TM-11-5805-688-14-10214

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

When the two transitions of the pulses occur at the same

output rate of the channel. When switch S5 is set to the

time, U25 determines that they are phase locked and

153.6K, 76.8K, 38.4K, or 19.2K position, switches S8

the output from U2 is effectively an open circuit. When a

and S12 are set to the 153.6K position. The selected

gated clock pulse to the write address counter is deleted,

out- put from U32 is applied through switch S5 and

U25 detects that the pulse from the read address

inverter U33-2 to the same circuits as those described in

counter is leading in phase the pulse output from the

the SB card theory of operation.

write address counter. Therefore, a series of more-

positive control signals is generated from U25 and is

applied to the active filter circuit. The pulses are

5-426. TRANSITION DECODER (TD) CARD.

continuous until a phase lock is obtained between the

two pulses applied to U25. In turn, when an additional

5-427. GENERAL. The TD card is a channel option

gated clock pulse is generated, U25 detects that the

card that may be used to service one digital data output

pulse from the read ad- dress counter is lagging the

channel that does not have associated timing. The

pulse from the write address counter. Therefore, a

function of the TD card is basically the complement of

series of less positive control signals replaces the normal

the function of the TE/TR card in the multiplexer.

phase-locked signal output from phase detector U25. In

Functionally, the TD card demultiplexes one selected

turn the less positive control signals are al plied through

channel of digital data out of the high-speed serial data

a low-pass filter circuit to voltage-controlled multivibrator

stream from the far-end multiplexer. The demultiplexed

(VCM) U26.

data are converted from a synchronous format to the

asynchronous digital format of their original application to

5-424. Resistors R8, R9, and R12 and capacitor C6

the far-end multiplexer. The block diagram discussion is

make up the low-pass filter. A series of positive pulses

based on the block diagram in figure FO-5. The de-

from U25 is filtered in the low-pass filter circuit into a

tailed circuit discussions are based on the TD card logic

positive-going dc slope voltage that is applied as a

diagram in the circuit diagrams manual.

control voltage and increases the output frequency from

VCM U26. In turn, a series of negative-going pulses

5-428. BLOCK DIAGRAM DISCUSSION.

from U25 is filtered into a negative-going dc slope

voltage that causes the output frequency from U26 to

5-429. Input-Output Buffer Function. The incoming

decrease. The out- put pulses from U26 are applied

digital channel data pulses (DTIX-) are clocked through

through inverter U20-15 to divide-by-16 counter U32.

the data in- put buffer to the data elastic storage register

by gated clock signals DGCXX. The gated clock signals

5-425. Four switches are involved in the operational

are also applied to the write address counter, which, in

configuration of the APLL circuit. Switch S7 in the input

turn, produces the 4-bit write address that is applied to

circuit of U26 is set to the NORM position during normal

the data elastic storage register and to the write ad-

operation. Switch positions MAX and MIN of S7 are

dress latch. The operation of the data elastic storage

used in the initial factory calibration of potentiometers

R14, R16, R18, and R73 in the VCM circuit. Switches

S8 and S12 are set to the 50K position when switch S5 is

set to the 50K position. Switch S5 is set to the nominal

Change 1 5-113