BLOCK DIAGRAM DISCUSSION - TM-11-5805-688-14-10205

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

The data are converted from a synchronous format into

circuits when the circuits are operated in the URD mode

the original asynchronous format that was applied to the

of operation. The write address counter, which is

far-end multiplexer. The original timing associated with

sequentially incremented by gated clock signals DGCXX,

the data is also regenerated.

The block diagram

generates the 4-bit write addresses that are applied to

discussions are based on the block diagram shown in

the data elastic storage register and to the write address

figure FO-4. The detailed circuit discussions are based

latch. The write address signals applied to the data

on the SB card logic diagram in the circuit diagrams

elastic storage register control the memory locations in

manual.

which the applied data bits are stored. The data elastic

storage register is identical to the data elastic storage

5-398. BLOCK DIAGRAM DISCUSSION.

read capability. The read address counter that generates

the 4-bit read addresses to the data elastic storage

5-399. GENERAL. The SB card can be operated in one

of two modes of operation. The mode of operation is

analog phase-locked loop (APLL) circuit. The data

controlled by setting the URD/SB switch to the URD or

clocked out of the data elastic storage register are

the SB position. The mode of operation is determined by

clocked through the data output buffer to the data output

the mode of operation selected for the far-end RCB card

drivers. The output clock signals that clock the data

in the multiplexer function. The system requirements

through the data output buffer are also generated by the

that control the mode of operation selected are described

APLL circuits. The timing output drivers are also clocked

in the RCB card discussion in paragraph 5-169. As

by the output clock signals from the APLL circuit. The

described in the following paragraphs, the basic

data and timing output signals are conditioned in the

operation of the SB card is the complement (or reverse)

output drivers and are routed through their associated

of the RCB card. The data elastic storage register in the

output line switch circuits that are set to produce a

SB card writes in the data under control of a

balanced or an unbalanced line output. When the output

synchronous clock and reads out these data under

is applied to a balanced line configuration, the output

control of an asynchronous clock. This synchronous to

data and timing line switches are set so that the two

asynchronous form conversion is accomplished using a

channel data out signals (DOXX and DOXX-) and the

smoothing function that produces output data bits at the

two timing out signals (TOXX and TOXX-) are

same rate at which the data were applied to the RCB

generated. In an unbalanced condition, only signals

card of the far-end multiplexer. This basic smoothing

DOXX and TOXX are generated. The end-of-scan

concept is described in paragraph 5-64.

activity detector samples end-of-scan signal DEOS3NX.

The detector is a retriggerable one shot multivibrator that

5-400. Input-Output Buffer Function. The incoming

is held in conduction by signals DEOS3NX. When the

channel data bits (DTIX-) are clocked through the data

signals are missing, the one-shot multivibrator duty cycle

input buffer by associated gated clock signals DGCXX.

expires and generates an inhibit signal that inhibits the

The gated clock signals are applied directly to the data

data output of the data output buffer.

input buffer in the SB mode of operation, or the signals

are processed through the coarse rate conversion

5-104