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T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3011
code store. In the frame maintenance mode, each 23-bit
loop arrangement as depicted in simplified form in figure
pattern containing seven or less errors causes the up/
5-9.
Under control of a gated clock (GC) signal
down confidence counter to be incremented by one
generated within the demultiplexer common electronics
count, and the frame sync latch to remain set. Each
section, data bits associated with a given channel are
received code containing more than seven errors causes
read from the serial data bus into the channel card
the up/down confidence counter to be decremented by
elastic storage register. The GC signal exactly matches
one count. If several successive codes containing more
the GC signal applied to the transmitting multiplexer
than seven errors are detected, the confidence counter is
channel card, and therefore may have individual clocks
decremented to 0 and the frame sync latch is reset to a
added or deleted as necessary to accommodate channel
loss-of-frame condition. In such an event, the frame
rate variations applied to the multiplexer's channel input.
acquisition mode is again automatically initiated.
Data in the demultiplexer channel card's elastic storage
register are read out under control of a clock provided by
5-63. Based upon the above discussion, it can be
a voltage-controlled multivibrator (VCM). Located on the
established that the demultiplexer frame synchronization
channel card, the VCM is configured to operate
function operates in two automatically selected modes:
independent of the GC at the channel's nominal output
acquisition and maintenance. Frame acquisition is
data rate, and also provides the channel's output timing
accomplished by a combined parallel and serial search
signal.
for one of the three overhead stuffing codes transmitted
by the multiplexer. Frame maintenance is achieved by a
5-67. Since there are variations in the rate of the GC
23 bit serial search for one of the three possible codes.
timing signal, the VCM and GC signals are phase locked
In either the acquisition or maintenance mode, a
to prevent underflow or overflow of the elastic storage
prescribed number of detected code errors may be
register.
A phase comparator determines when a
present without causing disruption of the overall frame
predetermined offset between the channel card's input
synchronization process. Further discussion of the
and output counters increases or decreases beyond
frame synchronization function is presented in
acceptable limits. When an unacceptable offset is
detected, the phase comparator yields a corresponding
error signal that is routed, via a filter/amplifier network, to
5-64.
SMOOTHING FUNCTION.
the frequency control input of the VCM. Thus, when the
input counter is determined to be operating faster than
5-65. When outputting data other than voice, channel
the output counter, the resultant error signal causes an
cards in the demultiplexer perform a synchronous-to-
increase in the VCM output frequency. In turn, when the
asynchronous buffering process that is the inverse of the
input counter is determined to be operating slower than
stuffing operation performed in the multiplexer. The
the output counter, the resultant error signal causes a
demultiplexer destuffing process results in reinsertion of
decrease in the VCM output frequency. The net effect is
those rate variations that were present at the transmitting
that the input counter and output counter timing sources
multiplexer's channel inputs.
are phase locked. Circuits within the filter/amplifier
network are
5-66. A smoothing function is also accomplished by an
analog
phase-locked
Change 1 5-18
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