FRAME SYNC (FS) CARD

T.O. 31W-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

timing signal Ro and multiplexer timing out signals

5-108. FRAME SYNC (FS) CARD.

TIMOUT and TIMOUT- are generated by the output

timing line driver. These timing signals are derived from

5-109. The FS card buffers the incoming high-speed

an external timing reference source that is applied

digital data and distributes the incoming data to all the

through the EXT position of the EXT/INT switch, or from

channel cards in the demultiplexer.

frame

a precision master oscillator on the RT card through the

synchronization function and an

overhead decode

INT position of the EXT/INT switch. In a balanced line

function are also performed on the FS card. The frame

configuration, the timing signals are transmitted as

synchronization function synchronizes the demultiplexer

complementary signals TIMOUT and TIMOUT-. In the

timing generation circuits to the timing associated with

unbalanced configuration, signal TIMOUT- is terminated

the incoming data. The overhead decode function

(grounded). The output timing line driver also generates

decodes one of the three stuff codes that are in the

system clock signal Ro that is identical to the TIMOUT

overhead message during each minor frame period.

signal. Signal is applied to the OEG card.

5-110. The incoming high-speed digital data stream

5-105. The timing recovery (TR) timing generation

(DATA) is applied to the data receiver circuits where the

circuits produce precision 3600-Hz and 4800-Hz timing

data are conditioned into the TTL levels that are

signals that are applied as timing signals T3600 and

compatible with the logic circuits in the demultiplexer.

T4800 to the TE/TR cards in the multiplexer.

The data for the data receiver are applied to the

channel data output shift register,

parallel sync

5-106. OVERALL DEMULTIPLEXER FUNCTIONAL

acquisition circuits, and

serial sync and sync

BLOCK DIAGRAM DISCUSSION.

maintenance circuits. The data are clocked through the

channel data output shift register by system input clock

5-107. GENERAL. A demultiplexer configuration uses

signals RIO from the timing receiver circuits. The shift

between one and 15 channel option cards to process up

to 15 channels of asynchronous digital data (with or

signal DFS from the serial sync and sync, maintenance

without timing) and/or voice data outputs to associated

circuits when frame synchronization is lost. In normal

communications links. The four types of output channel

operation, demultiplexer input data signals (DTIX-)

cards that can be used in the demultiplexer are the SB,

clocked through the shift register are routed to each

NBSB, TD, and VD cards. Five common cards used in

channel card in the demultiplexer,

the demultiplexer generate the

timing and control

signals for demultiplexing the applied high-speed serial

5-111. The parallel sync acquisition circuits establish

data stream from the far-end multiplexer. The OEG,

the initial synchronization of the demultiplexer timing

GC/DM, seq, FS, and ERD cards are the common cards

with she incoming data timing. The circuits search the

in the demultiplexer. The overall demultiplexer block

applied data for the first 11 bits of the overhead

diagram is shown in figure FO-2.

message located in bit 0 of the first 11 words. Since the

first 23 bits of the

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