SEQUENCER (SEQ) CARD - TM-11-5805-688-14-10128

T.O. 31W-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

overhead message contain one of the three fixed stuff

removed. This causes the channel data output shift

command codes, the first 11 bits are predictable and

can be identified. When the first 11 bits of one of the

circuits on the ERD card to be inhibited. At the same

three stuff command codes is identified, demultiplexer

time, removal of signal DFS also enables the parallel

frame sync signal DSYNC- is generated and applied as

sync acquisition circuits to start another initial frame

an enable signal to the serial sync

and sync

synchronization search. Assuming that the equipment

maintenance circuits. Signal DSYNC- is also applied to

and incoming signals are not in a permanent error

the seq card to synchronize the channel address

condition, signal DFS will again be generated and

generation circuits with the incoming data timing. The

maintained as long as a synchronous timing condition is

serial sync and sync maintenance circuits then monitor

present. The serial sync and sync maintenance circuits

overhead bits 12 through 23 in the overhead message

also generate demultiplexer overhead data signals DOD-

during the same minor frame in which bits 1 through 11

(bit 0 of each word) that are applied to the ERD card.

were identified. When overhead bits 12 through 23 are

As part of the sync maintenance function, the incoming

successfully identified as part of a given stuff command

stuff command code is decoded, and negative stuff

code, frame synchronization is effectively completed. At

enable signal DNSE or positive stuff enable signal

the time that signal DSYNC is applied, the serial sync

DPSE is produced. The absence of both signals during

and sync maintenance circuits produce demultiplexer

a minor frame period indicates the presence of the no-

word counter preset signal DWPR that is applied to the

action condition. These signals are applied to the

GC/DM card to synchronize the gated clock generation

GC/DM and ERD cards to initiate the appropriate

circuits with the incoming data timing.

stuffing action. Word 29 signal DW29 and end-of-scan

signals DEOS2 and DEOS2- are applied as part of the

5-112. Once frame synchronization is

established,

demultiplexer timing function.

demultiplexer frame sync signal DFS is generated and

applied as an enable signal to the channel data output

5-113. SEQUENCER (SEQ) CARD.

shift register and to the error rate detector circuits on the

ERD card. Signal DFS is also applied to the parallel

5-114. The seq card generates the channel address,

sync acquisition circuits as an inhibit signal that prevents

end-of-scan, and overhead DMF=PS signals that are

the circuits from being enabled again until frame

applied to the GC/DM card for timing purposes. The

synchronization is lost.

After

initial frame

PORT STRAPPING and PORTS IN USE switches on

synchronization, the serial sync and sync maintenance

the card are set to the same switching configuration as

circuits continue to check that one of the three stuff

that used on the seq card in the far-end multiplexer.

code patterns generated (during words 1 through 23) by

End-of-scan timing signals generated on the seq card

the stuff code generation circuits on the GC/DM card is

are also applied to the ERD and OEG cards.

the same as the stuff code pattern contained in the

incoming data overhead message format. When the

5-115. The channel address generation circuits on the

incoming pattern does not match one of the three

seq card generate 4-bit binary channel address signals

patterns from the GC/DM card,

an out-of-

DCHAD1 through DCHAD8. These signals, which are

synchronization state is identified and signal DFS is

generated at the system clock rate

5-27