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T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3011
Positive stuff multiplexers No. 1 (U3) and No. 2 (U4) are
Functionally, the sync acquisition circuits establish frame
only used in the diagnostic  function for  routing
synchronization when the equipment is initially energized
demultiplexer channel card errors to the display card.
and reestablishes frame synchronization when a loss of
Positive stuff request signals DPSTO1 through DPST15
frame  synchronization  is  detected  during  normal
contain the diagnostic error status of the channel cards
operation.
The frame sync maintenance circuits
in the demultiplexer. The error signals applied to U3 are
continually monitor for frame synchronization during
serially multiplexed into positive stuff acknowledge signal
normal operation. The functions performed by these
MPSA- that is applied to the display card.  Overhead
circuits are keyed to the stuff command code contained
address signals DOHO through DOH3 from the GC/DM
in bit 0 of words 1 through 23 of the overhead message
card contain the 4-bit channel addresses that select the
as described in the following paragraphs.
one channel card diagnostic input that is applied to
multiplexer U3 during each minor frame period.
5-476.  Overall FS Card Discussion (Figure FO-6).
The parallel sync acquisition circuits establish frame
5-471. Operation of the end-of-scan generation circuits
synchronization when the equipment is initially energized
and the word 24 generation is the same as that
and when frame synchronization is lost during operation.
described for the OEG card in the multiplexer. The
The input data pulses (DATA) are clocked through the
system clock signal circuits that generate system clock
input data shift register by its own externally applied
signals MRIO1- through MRI08- are not used in the de-
timing signals (TIM) to the variable length shift register
multiplexer application.  System clock activity detector
(VLSR). The VLSR temporarily stores 10 consecutive
U12 monitors demultiplexer input system clock signal RI
incoming data words and applies one bit at a time from
from the FS card and generates error signal DLOT-
each word (same bit number in each word) to the three
when the signal is missing.
code comparator circuits. Each of the three code
comparators per- forms an A=B compare search for the
5-472. FRAME SYNC (FS) CARD.
first 11 bits in one of the three stuff command codes
contained in words 1 through 11 in the incoming
overhead data message. The 11th bit (B11) is applied
5-473.  GENERAL.  The FS card is a demultiplexer
on- line (not stored) to an input on each of the three code
common card that performs a timing function and an
comparators.
overhead function. A frame synchronization function is
performed to synchronize the demultiplexer timing
5-477.
Before frame synchronization is obtained,
generation circuits with the incoming data stream timing.
signals Bl through B10 can be in any, bit location within
A stuff command decode function on the FS card
each of the 11 data words being sampled. The fixed B
decodes one of the three stuff command codes (negative
input to each code comparator circuit represents the first
stuff,  positive stuff,  or no action) contained in the
11 bits of the stuff command code with which it is
overhead message during each minor frame period.
associated. These codes are described in paragraph 5-
14. At the time that a compare is made in one of the
5-474. BLOCK DIAGRAM DISCUSSION.
three code comparators, B1 through B11 will contain bit
0 of words 1 through 11. At this time, the parallel sync
5-475. The overall simplified block diagram discussion
control circuits are activated.
for the FS card divides the circuits into two major circuit
groupings: the parallel sync acquisition circuits and the
serial sync acquisition and sync maintenance circuits.
5-123

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