APLL Circuit - TM-11-5805-688-14-10206

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545- 3011

these two signals are coincident at the phase detector

5-401. APLL Circuit. The write and read address

inputs, and the inversion of the write address MSB yields

counters are clocked by independently generated timing

the desired 8-bit offset. When an individual gated clock

signals. The write address counter is clocked by gated

pulse is added or deleted, the resulting phase shift

clock signal DGCXX, and the read address counter is

between the gated clock and VCM output signals is

clocked by the divided output of a voltage-controlled

detected by the phase detector, which produces a series

multivibrator (VCM). The APLL circuit phase locks the

of control pulses. These control pulses are applied to an

output of the VCM with the incoming gated clock signal,

active filter circuit, causing a gradual dc control voltage

causing the VCM to generate a number of read clock

change to be applied to the voltage-controlled

pulses equal to the number of write clock pulses being

multivibrator (VCM) input. The width of dc control

applied to the data elastic storage register over a given

voltages applied to the phase detector is proportional to

period of time.

A smoothing function is also

the degree of phase differential that is detected. The

accomplished by the APLL circuit. Gated clock pulses

greater the phase differential, the wider the width of each

are added and deleted as a result of the overhead

control pulse from the phase detector. In turn, as the two

servicing function. The addition or deletion of a gated

signals being compared by the phase detector approach

clock pulse represents an instantaneous change in the

an in-phase relationship, the width of the control pulses

applied gated clock frequency. Since synchronization

decreases and the pulses are turned off when the two

circuits of user equipment cannot operate with such a

signals are phase locked. This changing control voltage

change applied to their inputs, instantaneous bit rate

causes the VCM output frequency to slew to a rate

deviation is not acceptable. The APLL circuit therefore

nominally equal (after division by a divide-by-2n counter)

detects the instantaneous gated clock addition or

to that of the gated clock signal. In practical operation, a

deletion, and gradually (smoothly) increases or

continuous in-phase relationship is not maintained, but

decreases the output rate of the VCM by one bit time

continuous control pulses are generated that force the

over an extended number of VCM clock times. The

VCM output to slew near the gated clock pulse input rate

gradual change in VCM output rate causes the gated

and effectively maintain a pulse for-pulse relationship

clock and VCM rates to become nominally equal, while

over any given period of time.

precluding unacceptable short-term rate variations in the

channel's output timing signal. Thus, in performing the

5-403. Figure 5-31 conceptually depicts key APLL

smoothing function, the APLL circuit maintains a phase

waveforms and serves to illustrate overall APLL

locking of the gated clock and VCM output signals, and

operation. In figure 5-31, part A, a gated clock is deleted

prevents an underflow or overflow of data in and out of

from the U-18 write input (negative stuffing), causing the

the data elastic storage register.

dc control voltage to appear at the output of phase

detector U20. When applied to active filter U25, the dc

5-402. As in the RCB card, an 8-bit offset is maintained

control voltages cause the active filter to produce a

between the write and read addresses being applied to

negative-going change in the control voltage applied to

the data elastic storage register. This is accomplished

the VCM.

by applying the MSB of the 4-bit read address and the

inverted MSB of the 4-bit write address to the two inputs

of the APLL phase detector. In the locked condition,

Change 1 5-105