Simplified Block Diagram Discussion

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

When the input data rate meets the requirements of the

determine that the read address count leads or lags the

formula, switch S3 is set to the RCB position and the

write address count by more than the predetermined

circuits in the coarse rate conversion function are

offset, a positive (PSTXX) or a negative (NSTXX) stuff

bypassed as shown in figure 5-11 and as described in

command is generated and routed to the GC/DM card.

paragraph 5-172. When the input data rate does not

The stuff command causes the GC/DM card to either

meet the requirements of the formula, switch S3 is set to

add or delete gated clocks until the read address counter

the URC position. With S3 in the URC position,

properly tracks the write address counter. When the two

incoming gated clock signals GCXX are routed through

address counters are synchronized, a data bit is read out

the circuits in the coarse rate conversion function, where

for each data bit that is written into the elastic storage.

they are modified as described in paragraph 5-173.

The stuffing of gated clocks (adding or deleting clocks)

does not change the basic bit rate (KRp) at which the

5-170. Simplified Block Diagram Discussion (Figure 5-

gated clocks are being generated. The addition or

11).

deletion of gated clocks is performed as a part of the

multiplexer overhead service function.

5-171. The incoming data (DIXX) and the associated

timing signals (TIXX) are applied to receiver circuits that

5-173. Switch S3 is set to the URC position when the

process the digital data and timing to TTL levels that are

incoming data bit rate is greater than +250 ppm of KRp.

In this configuration, the gated clocks from the GC/DM

compatible with the digital circuits on the RCB card. The

card are routed through the coarse rate conversion

conditioned timing pulses from the receiver circuits

circuits and are then applied to the read address counter.

increment the write address counter, which, in turn,

A basic condition in this configuration is that the number

generates the write addresses for writing the conditioned

of used ports strapped together and the port rate

data into the elastic stores. The data pulses read out of

establish a KRp that is greater than the data bit rate

the elastic stores and applied to the output buffer are

being processed. In operation, the rate conversion

controlled by the read address counter, which is

functional circuits appear to convert the gated clock bit

incremented by gated clocks (CGXX) from the GC/DM

rate to the internal KRp sampling rate to obtain bit

card. One gated clock is applied to the read address

integrity between the asynchronous pulses applied to the

counter for each data bit applied to the RCB card to

elastic stores and the synchronous pulses out of the

maintain bit integrity while the data are processed.

elastic stores. Actually, the coarse rate conversion is

obtained by select deletion of individual gated clocks until

5-172. Switch S3 is set to the RCB position when the

the number of gated clocks is effectively lowered to

incoming data bit rate is within +250 ppm of KRp as

explained above. In this configuration, the incoming

produce the same number of clocks (KRp) that equal the

gated clocks are applied directly to the read address

incoming data bit rate (Rc). The modified gated clock bit

counter. The number of gated clocks applied to the RCB

rate from the coarse rate conversion circuits is applied to

card is controlled by the sample and control circuits that

the read address counter. Any positive or negative stuff

continually monitor the 4-bit address counts in the two

actions generated by the sample and control

address counters. When the sample and control circuits

5-40