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Page Title:
INTEGRATED CIRCUIT DESCRIPTIONS-CONT. |
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 T.O. 31S5-4-308-1
TM 11-5805-663-14-13
NAVELEX 0967-464-00-0010
(pin 7) is provided by OR gated propagate-
negative overflow carry pulse is generated
carry inputs (POPl,P2,P3). The active low
1 count in every 15 and they can be used
generate-carry output, G (pin 10) is pro-
to enable successive cascaded stages.
vided by OR'd AND gated generate-carry
When the enable input (pin 4) goes to a
inputs (GO, Gl, G2, G3). The carry out-
high level both up and down counting is
puts are provided by NCR'd AND gated
inhibited and the counter holds the binary
generate-carry inputs, propagate-carry
value of the last count. When the enable
inputs, and carry input (Cn) that is
input goes to a low level the counter. be-
generated by an up-stage ALU-SN74182N
gins to count again, beginning with the
stage. Carry output Cn+x (pin 12) is
stored last count (no reset).
derived from NCR'd AND gated carry input
(Cn), generate-carry input (GO), and
propagate-carry input (PO). Carry output
SETTABLE BINARY COUNTER/LATCHES (see
Cn+y (pin 11) is derived from NOR'd AND
figure 165). The SN74197N is a 4-bit pre-
gated generate-carry inputs (GO and Gl)
settable binary counter consisting of four
and carry input (Cn). Carry output Cn+z
d-c coupled, master-slave flip-flops
(pin 9) is derived from NOR'd AND gated
which are internally connected to provide
generate-carry inputs (Go, Gl, G2) and
a divide by two counter and a divide of
carry input (Cn). With the outputs from
eight counter. Presetting or loading of
the ALU's being in negated form, the
the counter is accomplished by placing a
Boolean expressions of each output given
low-level on the count/load input (pin 1)
holds true.
when the binary value from 0 to 15 is on
the data inputs (pins 3, 4, 10 and 11).
This action causes the four flip-flops to
COUNTER WITH UP/DOWN COUNT
store the binary value applied to the data
CONTROL (see figure 164). The
inputs and the outputs (pins 2, 5, 9 and
SN74191 is a presettable, synchronous,
12) will change to agree with the data
inputs regardless of the state of the clocks.
up/down, binary counter. Presetting or
Once the count/load input goes to a high-
loading of the counter is accomplished
level each successive high-to-low transi-
when a high-to-low transition occurs on
tion of the clocks (pins 6 and 8) increments
the load input (pin 11) when a binary value
the counter. Termination of the counting
on the data inputs (pins 1,
process is provided by an asynchronous
This action causes the
clear input (pin 13). Once the clear input
four J-K flip-flops to store the binary
value applied at the data inputs. If t
goes
low,
all
four
flip-flops
are
reset
(count of zero) regardless of the clocks
enabIe input (pin 4) is low and the load
and the count/load inputs- As the output
input goes high and if the down/up input
(pin 5) of the first flip-flop is not connected
(pin 5) is Pow each successive high-to-
to the succeeding flip-flops, the counter
Bow transition of the clock (pin 14) incre-
can operate in two independent modes.
ments the counter from the previous binary
value to the next higher binary value, id
the down/up input is high each successive
high-to-low transition of the clock incre-
ments the counter from the previous binary)
value to the next lower binary value. At
each count of 15 (all four flip-flops are
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