INTEGRATED CIRCUIT DESCRIPTIONS-CONT. - TM-11-5805-663-14-130183

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

without changing the contents of the

5-798. SN74175N, QUADRUPLE D-TYPE

FLIP-FLOPS WITH CLEAR (see figure 160).

The SN74175N is a 4-bit storage register.

5 - 8 0 0 . SN74181, ARITHMETIC LOGIC

Data at the inputs (pins 4, 5, 12, and 13)

UNIT/FUNCTION GENERATOR. (see

is transferred to the Q outputs (pins 2, 7,

figure 162). The SN74181 is an Arithmetic

10 and 15) and the compliment is trans-

Logic Unit (ALU) capable of performing 16

ferred to the Q outputs (pins 3, 6, 11 and

binary operations of two 4-bit words. The

14 on the positive-going edge of the clock

16 operations are selected by the four

input (pin 9). Once the clear input (pin 1)

function-select lines (SO, Sl, S2, S3)

goes low, all four flip-flops are reset,

with mode control input (M) high for logic

regardless of the levels of the clock and

operations and low for arithmetic opera-

data inputs. The four inputs are wired to

tions. The logic-function mode provides

the D inputs of each flip-flops and they

Exclusive-OR, Comparator, AND, NAND,

are clocked in parallel with clear input

OR, NOR, and ten other logic operations.

a l s o . With a 4-bit input, each bit is

The arithmetic mode provides addition,

loaded to a flip-flop on the positive edge

subtraction, shift operand A one position,

of the clock input and the flip-flops will

magnitude comparator, and twelve other

hold their loaded state till cleared or

arithmetic operations. Two cascaded out-

power recycled. The output can be taken

puts (pins 15 and 17) are available for

of the Q outputs of each flip-flop and also

direct connection with a SN74182N (look-

the complement of the Q outputs without

ahead carry generator) for high speed

altering the state of each flip-flop. The

look-ahead carry functions. Ripple-carry

truth table provided applied to each flip-

input (Cn) and a ripple-carry output (Cn+4)

flop.

are provided if high speed carry operation

is not needed. The subtracting function

5-799. SN74178, 4-BIT PARALLEL ACCESS

of the ALU is performed by l's complemented

SHIFT REGISTER. (see figure 161). The

addition and with l's complement subtra-

SN74178 is a d-c coupled high frequency

hend being generated internally. In the

(39 MHZ) 4-bit shift register able to oper-

Comparator mode, the ALU should be in

ate in three modes; synchronous parallel

the subtract mode with ripple carry (Cn)

load, right-shift, and hold. The clock

high. In this mode that A-B outputs (pin

input responds to a negative going trigger

14) is internally decoded from the function

and the four flip-flops are directly cleared.

outputs (FO, F1, F2, F3). With two words

It also has the D flip-flop providing Q

of the same magnitude applied to the A

output. Parallel loading is accomplished

and B inputs, the A=B output will go high

by taking the shift input low, applying

indicating equality. The 16 functions of

the four bits of data, and taking the load

the two Boolean variables (A and B input

input high. The data is loaded into the

words) that are selected by the four

associated flip-flop synchronously and

function-select lines are shown by the

appears at the outputs after a high-to-low

table with active high data inputs.

transition of the clock. During loading,

serial data flow is Inhibited. Shift right

IS also accomplished on the falling edge

5-801.

of the clock pulse when the shift input is

high regardless of the level of the load

input. Serial data for this mode is entered

at the serial data input. When both the

shift and load inputs are low, clocking of

the register can continue; however, data

appearing at each output is fed back to

t h e f l i p - f l o pinput creating a mode in

which the data is held unchanged. Thus,

the

system

clock ay be left free-running

5-131