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T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
(pins 3 through 6) and the load input (pin
input (pin 1). When the clear input goes
9) is low. This action causes the four
low, the first low-to-high transition of
J-K flip-flops to store the bin binary value
the clock input causes all four flip-flops
applied at the data inputs. Once the load
to reset (count of zero), regardless of the
input goes high and the enable inputs (pins
load or enable inputs.
7 and 10) are both received at high levels,
each successive low-to-high transition of
5 - 7 9 6 .  SN74170N, 4-BY-4 REGISTER FILE
the clock input increments the counter
(see figure 158).  The SN74170N is a
from the previous binary value to the next
4-word, 4-bit register file and decoding
binary value. At each count. of 15 (all
is provided for addressing the four word
four flip-flops are set), a ripple carry out-
locations to either write-in or retrieve
put (pin 15) is issued at a high level; at
data.  This permits simultaneous writing
the next count (zero) the ripple carry out-
into one location and reading from another
put goes low and remains low until the
word location. The four data inputs (pins
counter is again incremented to a count
1, 2, 3, 15) are used to supply the 4-bit
of 15. Thus a positive overflow carry
word to be stored. The write address in-
pulse is generated 1 count in every 15 and
puts (pins 13 and 14) in conjunction with
can be used to enable successive cascaded
the write enable (pin 12) determine the
counter stages. Termination of the
location of the word to be stored (see
counting process is provided by an asyn-
write truth table). Data applied to the
chronous clear input (pin 1). Once the
data inputs should be in its true form. If
clear input goes low, all four flip-flops
a high-level signal is desired from the
are reset (count of zero), regardless of
output, a high-level is applied at the data
the levels of the clock, load or enable
input for that particular bit location. The
inputs.
latch inputs are arranged so that new data
will be accepted only if both internal
5-795. SN74163N, SYNCMRONOUS 4-BIT
latch gate inputs are high. When this con-
COUNTER (see figure 157). The SN74163N
dition exists, data at the data input is
is a presettable synchronous counter.
transferred to the latch output. When the
Presetting or loading of the counter is ac-
write enable line is high the data inputs
complished when a low-to-high transition
are inhibited and their levels cause no
is applied to the clock input (pin 2) at a
change in the information stored in the
time when a  inary value from 0 to 15 is
internal latches. The read inputs (pins 4
received at the data inputs (pins 3 through
and 5) enable specific gates that deter-
6) and the load input pin is low. This
mine which word is to be selected for
action causes the four J-K flip-flops to
read-out.  The read enable input (pin 11)
store the binary value applied to the data
enables gates that pass the selected word
inputs.  Once the load input goes high
to the outputs (pins 6, 7, 9 and 10). When
and the enable inputs (pins 7 and 10) are
the read enable input is high, all data
both received at high levels, each suc-
outputs are high and remain high.
cessive low-to-high transition of the
clock input increments the counter from
the previous binary value to the next
5-797.
binary value. At each count of 15 (all
four flip-flops are set), a ripple carry
output (pin 15) is issued at a high level;
at the next count (zero) the ripple carry
output goes low and remains low until the
counter is again incremented to a count of
15.  T h u s a p o s i t i v e p u l s e i s g e n e r a t e d
one
in every 15 and can be used to
count
enable successive cascaded counter
stages.  Termination of the counting pro-
cess is provided by a synchronous clear

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