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Page Title:
INTEGRATED CIRCUIT DESCRIPTIONS |
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 T.O. 3155-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
allows selective clear/write and read/
IC is listed in table 5-1. The CM MSA
restore operations to be performed in one
provides the control and buffer logic, ad-
or both bytes within a given word.
dress decoding and switching, and X and
Y current source circuits of the C M BSM.
The control and buffer logic receives a
figure 134). The CM MBA (Switch:
select signal from CM MIA enabling it to
AlA8A3A1, AlA8P4A1, AlA8A5A1, AlA8A6A1,
control address switching and data flow
ACOC: AlA8A3A1, AlA8A4Al) contains the
from CM MMA core memory stack to CM
inhibit drivers and sense gates circuits of
MIB data register. The address decoding
the CM BSM. The inhibit circuit is
and switching circuitry receives the ad-
operative only during the restore portion
dress information from the CM MIA address
of read/restore mode and during the write
registers and decodes this information to
portions of the clear/write mode. The
turn on one set of X switches and one set
inhibit circuit is used when a zero is to be
of Y switches, resulting in current drive
written. Current is driven through the
through one X line and one Y line in each
sense/inhibit line, in the opposite direc-
plane of the CM MMA core memory stack.
tion from the current in the Y line, and of
X and y current sources for X and Y line
equal amplitude to that of the Y current.
drive are generated by a voltage regulator.
This causes the Y current to be algebra-
The voltage regulator, an operational ampli-
ically neutralized, core turn over does not
fier and related circuitry, supplies approxi-
core is left in the "0" state.
mately 3 volts dc.
s operate during the read
c y c l e s and receive information from the CM
memory stack via strobed ampli-
TIONS.
sense gates are controlled by
B.
5-775. HD-0165, KEYBOARD ENCODER
(see figure 137). The HD-0165 Keyboard
Encoder is a 16 line to 4-bit parallel en-
coder. It is used with manual data entry
devices such as a typewriter and codes
A5A2, AlA8A6A2.
each key input to a 4-bit binary code. The
H
165 has 16 input lines which are
normally wired through key switches of a
the Core Memory. The X and Y diode
matrices select individual X and Y lines in
man
data entry device to +Vcc. The 4-
the core memory stack. The core memory
tputs provide the binary code for
line
each of the input lines. The HD-0165
stack consists of 18 mats of 8K (8192)
cores each. Address information on X and
features a strobe output that is normally
Y lines is threaded through given cores at
used to gate the encoded signal to other
right angles to each other on all 18 mats
circuitry. The Strobe output may be condi-
so that a given address location specifies
tioned by external components to eliminate
switch bounce or skew in output propaga-
one core on each mat. Data information
on sense/inhibit line is threaded through
tion de lays. The output is high with no
input and goes
iven mat parallel to
all the cores on
en current is driven
address Y nine.
lines being high
along this Bane i
e opposite direction
KRO) output that
features a KEY R
from the direction of the Y current, the Y
is always high
current is algebraically cancelled.
5-773. CM MSA
A8iUA3) contains one
unique type of IC (type SN74145). T
applicable paragraph describing this unique
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