PRINTER CONTROLLER-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

the SWB are 62 momentary switches, 65

current

operation commands and the status

light emitting diode (LED) indicators, and

holds Serial I/O and VF Comm

three hidden accessible toggle switches

status. The Modem Controller 2

Link 2

for program debugging. When enabled, it

is used

only in the ACOC Group Processor.

is capable of sending switch closures to

the Program Maintenance Panel logic

5 - 7 6 6 . PBI (8033 1250-000) (see figure

which drives the indicators and provides

129). The PBI (Switch: AlA3A20, ACOC:

interface with the INFIBUS. Operating in

AlA3A17) contains three unique types of

the master mode it can communicate via

IC's (type SN74161J, SN74175N, and

the INFIBUS with any other addressable

NS74197N). The applicable paragraph de-

system module such as CPU, memories,

scribing these unique IC's are listed in

or peripheral device controllers. In the

t a b l e 5-l. The PBI, in conjunction with

slave mode other systems modules can

the PCB and SWB, forms the Program

access the Program Maintenance Panel via

Maintenance Panel. The PBI provides the

the INFIBUS. If data on the INFIBUS that

logic and interface between the Program

is addressed to the Program Maintenance

Maintenance Panel and INFIBUS enabling

Panel, conflicts with information stored in

the Program Maintenance Panel to gain

the Program Maintenance Panel, the data

INFIBUS access. The PBI provides control

from the Program Maintenance Panel is

logic, timing, micro operations, and bus

always retained.

driver/receiver circuits. The timing cir-

cuits consist of clock, state generation

5 - 7 6 9 . CM MIA (80332060-000) (see

and a control register. The Micro opera-

figure 132). The CM MIA (AlA8Al) contains

t i o n s circuit controls INFIBUS access logic,

the timing and control logic, address regis-

address recognition, and address compari-

ter and reset circuits of the Core Memory.

son.

The timing and control logic receives the

control signals from the Processor and

PCB (80331260-000) (see figure

5-767.

generates internal timing signals which con-

130). The PCB (Switch: AlA3A21, ACOC:

trol all functions in the Core Memory. The

AlA3A18) contains eight unique types of

address register receives 15 address bits

IC's (Type SN7493A, SN74150P, SN74154N,

from the Processor. Bits 0 to 6 are X ad-

SN74157N, SN74175N, SN74198N,

dress and bits 7 to 12 are Y address. Bits

N8266B, and HD0165). The applicable

13, 14 and 15 at-c decoded to produce C

paragraph describing these unique IC's

BSM select signals. The reset circuit pre-

are listed in table 5-1. The PCB in con-

junction with the PCI and SWB forms the

vents accidental loss of data in event of

Maintenance Panel which provides the

power failure, providing an orderly shut

logic and interface between the Program

down sequence and ensuring that the cycle

Maintenance Panel and INFIBUS. The PCB

in progress is properly completed.

provides the Program Maintenance Panel

SWB switches and indicators with the

CM MIB (80331370-000) (see

5-770.

necessary registers and drivers. The PCB

figure 133). The CM MIB (AlA8A2) provides

sends and receives data to and from the

the data register and zone control circuits

INFIBUS via strobed bus driver/receivers.

of the Core Memory. The data register

Also contained in the PCB are switch

consists of 18 flip-flops, one for each

system bit. Gated by signal +SAS and

identification, shift register, address re-

cognition and address comparison circuits.

reset by timing signal +RDR the data regis-

ter receives and stores information from

the CM MMA core memory stack until it is

strobed to the data output lines and/or

restored in the core memory stack. The

data register also stores incoming infor-

mation from the data input lines during

write operations. Zone control is opera-

tive during the clear/write write cycle and

5-125