PC CARD DESCRIPTIONS

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

AVELEX 0967-464-0010

5-754. CPB (80331220-000) (see figure

control register that controls the CPU

1 1 7 ) . The CPB (AlA3A6) contains nine

halt and run modes of operation.

unique types or IC's (type SN7415OP,

SN7415lAJ, SN74153N, SN74163N, SN74174N,

5-755. CPA (80331230-000) (see figure

SN74175N, P3205, N8264N, and N8235N).

118). The CPA (AlA3A7) contains eight

The applicable paragraph describing these

unique types of IC's (type SN74150P,

unique IC's are listed in table 5-1. The

SN74153N, SN74170N, SN74174N,

CPB, in conjunction with a matched CPA,

SN74175N, SN74181, SN74182N, and

form the CPU which is used to process

SM74198N). The applicable paragraph

a that is received from either the Core

describing these unique IC's are listed

mory or other Processor modules under

in table 5-1. The CPA in conjunction with

control of stored software programs. The

a matched CPB form the CPU which is

CPB contains microcode control circuits

used to process data that is received from

of the CPU. The microcode control circuit

either Core Memory or Processor modules

consists of three registers (E, S, and M)

under control of stored software programs.

a read-only-memory (ROM) control storage

The CPA contains the INFIBUS interface

unit, and the microcode control logic.

and arithmetic register sections of the

The E register stores 16-bits of data to be

CPU. The INFIBUS interface section

supplied to the microcode control logic.

consists of INFIBUS access logic and

Fields in this register correspond to the

three registers (address, receive, and

microcode instruction word format and

transmit).

e INFIBUS access logic

specify the instruction code, addressing

provides interface between the INFIBUS and

mode, general register (RI t

CPU by providing control logic as well as

index register, and occasionally a literal

address recognition logic. The three

operand. The S register is a 12-bit counter

registers are gated to the arithmetic

that sequences microsteps, addresses the

control storage and is under control

operations. The arithmetic logic section

of the microcode word. The M register

consists of a multiplexer, arithmetic logic

s t o r e s t h e 3 6 - b i t m i c r o c o d e t h a t specifies

unit, and a register file. The multiplexer

action-a of the current microstep as well as

selects an operand from one of three

control of the next microstep. The read-

registers or a 16-bit input data word.

only-memory control storage unit contains

ord is separated

microcode control words whic

Each field is

in ROM'S. The ROM's form a

r disabled as an

256-word read-only-memory consisting of

logic unit under

nine 256 by 4-bit LSI microcircuits. The

microcode control. The arithmetic logic

unit responds to commands from the CPB

36-bit microcode word contains 13 fields

for specification Of control functions

microcode word. These commands specify

within the Processor and selection of

which one of 16 logical operations or

operands. A variety of conditional test

which one of 16 arithmetic operations is

and skip or branch microsteps are pro-

to be performed. The register file consists

vided in the the field allowing conditional

of 12 16-bit registers.

coding to minimize the number of micro-

steps required per function. `The micro-

5-756.

code control Logic contains buffers, delay

circuitry, clock generators, and gating

Core Memory Controller (AlA3A8

necessary to control access to the ROM

and controls signal transfers to the

aritmetic register sect

This section

also provides a ""look a

feature that

allows the CPU, under macrocode control,

to access the next microstep while

executing the present step. Also includes

in the microcode control logic is a

5-122