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Page Title:
ADDRESS REGISTER, DECODING, SWITCHING, AND CONTROL AND BUFFER LOGIC CIRCUIT-CONT. |
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 T.O. 31S5-4-308-1
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
select signal generated determines which
ers 14 and U16. Address
address
CM BSM will be enabled. The following
7-P through
decoder U14 decodes
discussion assumes that CM BSM 1
ne of the output lines
(BSMOO-P generated) will be enabled.
The SASOO-P output of G1 activates gate
G2 which is also enabled by BSMOO-P.
5-745. A single sense/inhibit line threads
Address decoder U16
through all the cores correspondin
data bit. The sense circuitry f
data bit is identical, therefore
ing discussion discusses only t
tion of the 00 bit. During a read cycle,
to generate a positive pulse on the
the coincident X and Y currents cause the
selected line, YSOO-P through YSO7-P.
turn-over of a single core if a 1 has been
YS line selects a group of 8 lines out
stored. This turn-over induces a
groups and the YCC line selects one
approximately 30mv across the S-
line of the group of and allows Y write
lines. This pulse is shaped by t
current to flow through the selected Y core
shaper CRl, CR2, and U2 a
line from the YCC line to the YS line.
through the impedance matc
When X and Y write current flows through
Ul to the input of the differ
the selected core a 1 is stored into the
core if the sense/inhibit line does not
receiver U3.
have inhibit current flowing.
U3 converts the low level ou
core (S-00) to digital levels
SENSE, INHIBIT, A
The pulse output of the diffe
CIRCUIT.
receiver activates G3.
5-743.
During a read cycle,
5-746.
(waveform A, figure 115) activa
uit detects t
0 which activate gates G9 and G17 re-
data register stores this information until
spectively. The output of G9 enables
it is routed to the Processor and/or re-
gates G11, Gl2, and Gl3 and t
shred into core. The data register also
of G17 enables gates G18, G19,
stores incoming data from the Processor
The output of G7 is coupled through driver
during a write cycle. This inco
DRl which activates G12 and G1
is gated into the
ta register and the
ating DOXl-P and DOX2-P, respectively.
inhibit drivers ge
RDR-P (waveform B, figure 115
all dates bits that
G11 and G18 which generate R
current, when present, r
in the opposite
respectively.
SAOO-P through SA17-P to the dat
as MDROO-N through MDR17-N.
operate in exactly the same manner; there-
fore, the following discussion will discuss
the operation of data register
through
08. When RDRl-N goes low,
R1-N is
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