ADDRESS REGISTER, DECODING, SWITCHING, AND CONTROL AND BUFFER LOGIC CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

setting FF2. The 0 output of FF2 is in-

the output lines to go low. This low level

verted by inverter I2 which generates

is applied to the pulse transformer which

MAR06-P. AI13-P, AI14-P, and EI15-P

causes the transistor switch to generate a

are inverted by inverters I3, I5, and I7.

positive pulse on the selected line,

YCAOO-P through YCAO7-P. Address

The outputs of I3, I5, and I7 are clocked

into FF3, FF4, and FF5 on the leading edge

decoder U21 decodes MAR10-P through

of AM-P. The outputs of FF3, FF4, and

MAR12-P causing one of the output lines

FF5 are applied to the BSM select decoder

to go low. This low level is applied to

the pulse transformer which causes the

U39, U40, and U41 which generates the

transistor switch to generate a negative

required BSM select signal, BSM00-P

through BSMO4-P, to enable the selected

pulse on the selected line, YSOO-P

through YSO7-P. The YS line selects a

CM BSM. The following discussion

group of 8 lines out of 8 groups and the

assumes that the first BSM is being selected

YCA line selects one line of the group of

(BSMOO-P high).

8 and allows Y read current to flow through

the selected Y core line from the YS line to

5-740. During a read cycle, PRE YRT-P

the YCA line. The Y core line is threaded

(waveform B, figure 113) activates gate G2

through 18 cores, one in each mat. When

which determines the leading edge of

X and Y read current flows through the

YRT-N (waveform D, figure 113). MRT-N

selected core and if the core is in a 1

(waveform C, figure 113) is inverted by

state, the core turns over (returns to 0

inverter I6 which determines the trailing

state) generating a pulse on the sense/

edge of YRT-N. The output of I6 also acti-

inhibit line.

vates gate G3 which generates XRTl-P.

The output of G3 also activates gate G4.

Address decoder U17 is enabled by the out-

5 - 7 4 1 . During a write cycle, MWT-P

put of G4 and decodes MAROO-P through

activates gate G5 which generates WTl-P

MAR02-P causing one of the address decoder

(waveform E, figure 113). WTl-P is

output lines to go low. This low level

inverted by inverter I8 which enables

is applied to the pulse transformer which

address decoder U13. Address de-

causes the transistor switch to generate a

coder U13 decodes MAR00-P through

positive pulse on the selected line, XCAOO-P

MAR02-P causing one of the address

through XCAO7-P. XRTl-P enables G8 and

decoder U13 output lines to go low. This

G9 and if MARO6-P is high the output of

low level is applied to the pulse trans-

driver DR2,

06-P, is high, G9 is acti-

former which causes the transistor switch

vated which enables address decoder U23.

to generate a negative pulse on the

If MAR06-P is low the output of inverter

selected Sine, XCC00-N through XCCO7-N.

I4 is high, G8 is activated which enables

WTl-P enables G6 and G7 and if MAR06-P

address decoder U19. Address decoders

is high the output of DR2 is high, G6 is

U19 and U23 decode MARO3-P through

activated which enables address decoder

5-P and cause one of 16 outputs to

U24. If MAR06-P is low the output of J4

go low. This low level is applied to the

is high, which activates G7 enabling

sformer which causes the transis-

address decoder U15. Address decoders

to generate a negative pulse on

U15 and U24 decode MARO3-P through

the selected line, XSOO-P through XS15-P.

MAR05-P and cause one of 16 outputs to

The XS line selects one group of 8 Pines

go low. This low level is applied to the

out of 16 groups and the XCA line selects

pulse transformer which causes the

one line of the group of 8 and allows X

transistor switch to generate a positive

read current to flow through the selected X

pulse on the selected line, XSOO-P through

core lime from the XS line to the XCA line.

XS15-P. The XS line selects a group

of 8

The X core line is threaded through 18

Pines out of 16 groups and the XCC line

c o r e s , owe in each mat (each mat has 8192

selects one line of the group of 8 and

c o r e s ) . YRT-N enables address decoders

allows X write current to flow through the

UI8 and U2I. Address decoder Ul8 decodes

selected X core line from the XCC line

7-P through MAR09-P causing one of

to the XS line. WT2-N also enables

5-118