ADDRESS REGISTER, DECODING, SWITCHING, AND CONTROL AND BUFFER LOGIC CIRCUIT

T.O. 315-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

gates G20 and G23 are reset at 320 nsec.

conditions RD INIT-P (waveform AB, figure

The leading edge of MWT-P (waveform 2,

111) is gated through G4 to set FFl arid

figure 111) is determined by T200-P and

FF4. Operation is similar to the clear/

trailing edge by T260-P. MWT-P is ap-

write mode except setting FF4. enables

plied to the address register, decoding,

single shot SS2. SS2 generates a 100 nsec

switching, and control and buffer logic

pulse when RD PHS-P (waveform AC, figure

circuit, resulting in the generation of X

111), T260-P, and T140-P are logic 1.

and Y write currents.

The output of SS2 activates gate G18 which

generates DATA AVAIL-N (waveform AD,

figure 111) notifying the Processor that

5-733. CLOCKl-P triggers FF5 through

d a t a i s a v a i l a b l e . The logic 1 output of

FF8 and CLOCK2-P triggers FF9 through

FF10, RR-P/CW-N, also enables the sense,

FF12. At the start of each cycle the 0 out-

i n h i b i t , a n d d a t a c i r c u i t . MSAS-P now

puts of FFS through FF12 are logic 0 (pre-

causes the data to be strobed out of the

s e t ) . The first CLOCKl-P pulse clears FF5,

Core Stack (read mode) and into the data

the second CLOCKl-P pulse clears FF6 and

registers of the sense, inhibit, and data

so on until FFS through FF8 are cleared.

circuit. TINH-P and MWT-P cause this

The 0 output of FF8 is now logic 1 and the

data to be restored into the cores.

continuing clock pulses set FF5 through

FF8. FF9 through FF12 operate in the same

5-737. ADDRESS REGISTER, DECODING,

manner as FFS through FF8.

SWITCHING, AND CONTROL AND

FF5 through FF12 produce a series of

BUFFER LOGIC CIRCUIT.

timing pulses at 20 nsec intervals (wave-

forms E through Q, figure 111).

5 - 7 3 8 . G e n e r a l . The address register,

decoding, switching, and control and

5 - 7 3 4 . When FFl sets, the 0 output acti-

buffer logic circuit stores address bits 00

vates gates G15 and G16. The output of

through 15. Address bits 00 through 06 are

G16 activates gate G17 causes MEM AVAIL-P

X address bits and address bits 07 through

(waveform R, figure 111) to go to logic 0,

12 are Y address bits. Address bits 00

informing the Processor that the Core

through 12 select the CM BSM core memory

Memory is not available. The output of

stack address where the data is to be

G15 is delayed 50 nsec by delay DL2

stored. Address bits 13, 14, and 15 are

which activates gate G10 disabling gates

decoded to produce the various BSM select

G4, G7, and G8. At 550 nsec, single

signals.

shot SSl is triggered by T260-P and

T340-P causing its output to go to logic

5-739. Detail Analysis (See figure 112).

0 for 200 nsec. At 600 nsec, gate G9 is

The address register functions as an open

activated by T300-P and T180-P which

latch for address bits AIOO-P through

clears FFl and disables the oscillator (G6).

AIOS-P and AI07-P through AI12-P. Flip-

Clearing FFl presets FF5 through FF12.

flop FFl is reset at the end of a memory

The output of SSl holds MEM AVAIL-P at

cycle by CYC END-N. If AIOO-P goes high

logic 0 and disables G4 and G7 via'

when FF1 is reset the output of gate G1

G15, DL2 and G10 until the output

goes low which is inverted by inverter I1,

of SSl returns to logic 0.

causing MAROO-P to go high. 40 nsec

later T200-P goes low presetting FFl which

5-735. Gates G36, G37, and G38 and

causes the high output of inverter I1 and

delays DLS and DL6 generate MSAS-P

the 1 output of FFl to hold the output of

(waveform AA, figure 111) whose leading

G l l o w . The 1 output of FFl prevents any

edge is determined by T200-P and trailing

changes in AIOO-P from effecting G1. At

edge by T80-P.

the end of a memory cycle CYC END-N

goes to logic 0 for 33 nsec resetting FFl

5-736. In the read/restore mode WT INIT-P

which enables G1 again. AIO6-P is

and RD ONLY-P are logic 0 and FULL CYC-P

clocked into flip-flop FF2 on the leading

and MEM SEL-P are logic 1, under these

edge of AIX-P (waveform A, figure 113)

5-117