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Page Title:
ADDRESS REGISTER, DECODING, SWITCHING, AND CONTROL AND BUFFER LOGIC CIRCUIT-CONT. |
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 T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
high and DIXl-P is low, causing the output
driver U13, 1Q1, does not generate
of gate G24 to go high. At this time
inhibit current, INHOO-N. This causes
DOXl-P is high and the output of G24
the coincident X and Y current to store a
activates gate G22 which causes DOOO-P
1 at the address location. If a 0 is to
to go low. The high output of G24 is
be restored (DATA INHOO-P is logic 1)
applied to gate G25 which, with DIRl-N
G28 is enabled and strobed by TINHl-P
high, causes the output of G25
causing the output of G28 to go low. When
to go low. The low output of G25 is
the output of G28 goes low, driver U13,
applied to G24 to hold the output of G24
1Q1, generates inhibit current; INHOO-N,
high. The low output of G25 is also
which is driven through the sense/inhibit
inverted by inverter I5 which causes
line, C-00, in the opposite direction from
the current in the Y line. This causes the
DATA INHOO-P to go high. After the data
Y current to be algebraically neutralized
register is reset, RDRl-P returns to high
which enables G24. If a 0 is read from
and the core remains in the zero state.
the core (SAOO-P low), MDROO-N is high
and the data register does not change
5-748. During a write cycle, RR-P/CW-N
s t a t e . If a 1 is read from core, MDROO-N
is logic 0 and ZWl-P and ZW2-P are logic
is low which is applied to the output of
1. RR-P/CW-N is inverted by I2 which
G24 and the input of G25 which changes
activates G8 and G15. The output of G8
the state of the data register. When
enables G10 and the output of G15 enables
MDROO-N goes low, G22 is disabled,
G16. DIX-P (waveform E, figure 115),
which causes DOOO-P to go high.
from the timing and control logic circuits,
MDROO-N also disables G25 which
activates GlO and G16 causing DIRl-N
activates G24 which holds G22 disabled.
and DIR2-N to go to logic 0. DIRl-N is
The high output of G25 is inverted by
inverted by inverter I1 and DIR20N is
I5 which causes DATA INHOO-P to go low.
inverted by inverter I3 causing DIKl-P and
DIX2-P to go to logic 1. DIOO-P IS inver-
5-747. During a restore cycle TINH-P
ted by inverter I4. When DIOO-P is high,
(waveform D, figure 115) is generated by
the output of I4 is low which disables
the timing and control logic circuit,
G 2 5 . The high output of G25 is inverted
activating gate G29 which is enabled by
by I5 which causes DATA INHOO-P to go
BSMOO-P. The output of G29 is inverted
l o w . DATA INHOO-P low prevents inhibit
by inverters I8, I9, and I10 which strobe
current, INHOO-N, from being generated,
the data inhibit drivers. SPWR-P
allowing a 1 to be stored in core as ex-
activates gate G30 turning on transistor
plained previously. If DIOO-P is low, the
output of I4 activates G25 (DIXl-P logic 1).
switches Q2 and Q3 which generate
SVSl-P and 5VS2-P. 5VSl-P and 5VS2-P
This low output of G25 is inverted by I5
allow inhibit current to flow through the
causing DATA INHOO-P to go high which
generates inhibit current, INHOO-Ni
sense/inhibit lines of the core stack. If
causing a 0 to be stored in core, as ex-
the data to be restored is logic 1 (DATA
plained previously.
INHOO-P is logic 0), G28 is disabled and
5-120
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