PROGRAM MAINTENANCE PANEL INFIBUS ACCESS LOGIC CIRCUIT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

INFIBUS access circuit. The output

5-716.

PROGRAM MAINTENANCE PANEL

of G27 is routed to G28 which is disabled

INFIBUS ACCESS LOGIC CIRCUIT.

by FACR-N. CFOA-P activates G37 causing

OFCP-P to clear FF7 and FF9. Because

5 - 7 1 7 . General. The Program Maintenance

state generator U34 is now in its quiescent

Panel INFIBUS access circuit detects when

state (all outputs low), all operations in

the Program Maintenance Panel state gen-

the Program Maintenance Panel state

eration and micro operations circuit is re-

generation and micro operations circuit

questing an INFIBUS access for a direct

cease until the run or step switch is

data transfer and causes the direct data

touched.

transfer to occur. These circuits also

detect when the state generation and

5-714. When the attention, attn, switch

micro operations circuit is requesting a

on the Program Maintenance Panel mis-

level 1 interrupt to be generated and gen-

cellaneous control circuit is touched the

erates the level 1 interrupt. If the func-

Program Maintenance Panel INFIBUS access

tion addressing the Program Maintenance

circuit generates a level 1 interrupt. In

Panel is writing into the Program Mainte-

addition, the Program Maintenance Panel

nance Panel, the Program Maintenance

state generation and micro operations cir-

Panel INFIBUS access logic circuit also

cuit causes the Program Maintenance Panel

causes the information on the INFIBUS

address, FF80 16, to be strobed to the

data lines to be displayed by the address

INFIBUS data lines when INFIBUS access

or data LEDS. If the function addressing

is gained. When the attn switch is touched,

the Program Maintenance Panel is reading

FlSS-P goes high and, if an address recog-

from the Program Maintenance Panel, the

nition has not occurred (SARO-N high),

information from the address shift register

G50 is activated causing VADB-P to go

or data shift register is strobed to the

high. With RNDB-P and HTDB-P low and

INFIBUS data lines.

VADB-P high, the Program Maintenance

Panel address is strobed to the INFIBUS

5-718. Detail Analysis (see figure 108).

data lines when INFIBUS access is gained.

When the Program Maintenance Panel state

generation and micro operations circuit

5-715. When the Program Maintenance

receives a master reset pulse, MRES-N,

Panel is operating in the slave mode,

MREU-N goes low for the duration of

RO-N goes low when the Program Mainte-

MRES-N. MREU-N clears flip-flops FF3,

nance Panel address multiplexer, bus

FF6, FF9, FF10, FF12, and FF14, acti-

driver receiver and recognition circuit de-

vates gate G15 which resets flip-flop FF4,

tects the Program Maintenance Panel ad-

activates gate G18 which resets flip-flop

dress on the INFIBUS address lines.

FF5, and activates gates G16 and G35.

The output of G35 is inverted by inverter

SARO-N disables G49, G50, and G51

I14 which clears flip-flop FF13. The out-

which causes RNDB-P, VADB-P and HTDB-P

put of G16, RFlS-N, activates gate G25

to remain Pow. SARO-N is also Inverted

which clears flip-flop FF8. With FF6 and

by inverter I22 whic enables G52. The

FF8 cleared, gate G24 is activated which

output of I22, SARP-P, is routed to the

clears flip-flop FF11.

Program Maintenance Panel INFIBUS ac-

cess circuit to enable either the information

5 - 7 1 9 . When the Program Maintenance

determined by the address switches or by

US access circuit is required

e data switches to be strobed to the

INFIBUS data lines. If AOIA-P is low,

igh and the information deter-

mined by the address switches is strobed

to the INFIBUS data lines. If AOIA-P is

high, G52 as activated and DRDB-N is low,

and the information determined by the data

switches is strobed to to the INFIBUS data

lines.

5-112