PROGRAM MAINTENANCE PANEL SWITCH FLIP-FLOPS AND SINGLE ACTION DISGRIMINATOR CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

and G10 is activated which presets FF7.

second FRDS-P pulse also enables G23

The output of FF7 enables gate G14 which

which is activated a second time by CFOA-P

is activated by CFOA-P. The output of

when FSAS-P is high. The output of G23

G14 presets FF9 which enables G13 and

now ensures FF12 is cleared and FF13 is

causes FCPR-N to go low. FCPR-N acti-

s e t . The above action continues as long

vates G4 and the output of G4 activates

as only the address read switch is touched.

G5. The next positive going edge out of

I3 triggers state generator U34 causing

5 - 7 1 0 . When the register write switch on

FSBS-P to go high and FSBR-N to go low.

the Program Maintenance Panel is touched,

The output of I2, FSBR-N, presets FF5

operation is similar to when the halt switch

which disables G5. The positive going

is touched, except FWGR-N goes low.

edge out of I3, after FF5 is preset, triggers

When FWGR-N goes low G53 is activated

state generator U34 causing FSBS-P to go

which enables G52. FW1S-P activates

low and FSBR-N to go high. While FSBS-P

G52 causing DRDB-N to go low. With

is high and FSBR-N is low, OFDN-N,

ARAB-P low and CRAB-N high, the address

lFND-N, and FWlS-P are generated, as

determined by the reqister 0 through 15

explained previously. Also while FSBS-P

switches is strobed to the INFIBUS address

is high, G15 is activated by CFlA-P which

lines when INFIBUS access is gained.

clears FF8. G15 is then activated by

With RNDB-P, VADB.-P, HTDB-P, and

CFOA-P which presets FF8. FF8 remains

DRDB-N low, the data determined by the

set until the next FSBS-P pulse is gener-

data 0 through 15 switches is strobed to

ated. When FACR-N goes low, G57 and

the INFIBUS data lines when INFIBUS ac-

G58 are activated. The output of G56 en-

cess is gained.

ables G51 (SARO-N high) and the output of

G58 enables G59. When FWlS-P goes

5 - 7 1 1 . When the resister read switch is

high G51 and G59 are activated causing

touched, operation is similar to when the

halt switch is touched, except all signals

HTDB-P to go high and CRAB-N to go low.

Under these conditions the CPU control

from the Program Maintenance Panel switch

flip-flops and single action discriminator

circuit are inactive and ANRW-N is gener-

strobed to the INFIBUS address and data

lines, respectively, when INFIBUS access

ated. With these signals inactive, ARAB-P

is gained.

is low and CRAB-N is high which causes

the address determined by the resister 0

through 15 switches to be strobed to the

5 - 7 1 3 . When the Program Maintenance

INFIBUS address lines when INFIBUS access

Panel INFIBUS access circuit receives

is gained. Also, with these signals in-

DONE-N or QUIT-N from the CPU, FNDR-N

active RNDB-P, VADB-P, and HTDB-P are

or FATR-N goes low. FNDR-N or FATR-N

low and DRDB-P is high which prevents

activates G3 which activates G2. The

any data from being strobed to the INFIBUS

next positive going edge out of I3, after

data lines when INFIBUS access is gained

FNDR-N or FATR-N goes low, triggers the

and the addressed CPU register places its

state generator U34 which causes FSCS-P

data on the INFIBUS data lines. This data

to go high. FACS-P is enabling gate G37

is displayed by the data 0 through 15 LEDS.

and FACR-N is disabling gates G28, G36,

and G44. FSCS-P activates G27 and G40.

5 - 7 1 2 . When the address halt, adh, switch

The output of G40 is inverted by I17 causing

is touched, FAHS-P goes high and if the

OFWl-P to go high which clears FF2 and

Program Maintenance Panel is not strobing

ensures FF1 is cleared. The output of FF1

information to the INFIBUS, STRE-P and

now disables G2 and the next positive

STRD-P are low. When STRE-P and STRD-P

going edge out of I3 causes FSCS-P to go

are low, gate Gl2 is disabled and the high

low. The output of G40 also activates

output of inverter I10 and FAHS-P enables

G38 which enables G39 to, be acti-

gate G10. When the address on the infibus

vated by CF-lA-P. The output of G39,

is the same as the address determined by

the second OFDN-N pulse is routed

the address switches, EOA4-P goes high

to the Program Maintenance Panel

5-111