PROGRAM MAINTENANCE PANEL SWITCH FLIP-FLOPS AND SINGLE ACTION DISGRIMINATOR CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

107) to go high and FSDR-N to go low.

INFIBUS access is gained. With DRDB-N,

FSDS-P activates G40 which activates G38,

RDNB-P, VADB-P, and HTDB-P low, the

enabling G39. CFlA-P activates G39,

data determined by the data switches is

generating the third OFDN-N pulse. The

strobed to the INFIBUS when INFIBUS ac-

output of G40 is inverted by I15, generating

cess is gained. This action causes the

data displayed to be written into the ad-

the second OFWl-P pulse which resets

FFl and FF2. FSDR-N activates G29, G42,

dress displayed. FWRS-P is routed to gate

and G46. The output of G46 goes low and

G19 which is permanently disabled by in-

verter I12. FWRS-P also enables gate G26

is routed to the Program Maintenance Panel

switch flip-flops and single action dis-

which is activated by CFOA-P when FSAS-P

criminator circuit. The output of G42 goes

is high. The output of G26 ensures FF12 is

low which clears FF5. When DONE-N or

set and clears FF13. However, because

QUIT-N was received FDNS-P went high,

G19 is disabled no further action occurs.

enabling G30. The output of G29 (high)

5 - 7 0 9 . When the address read switch on

also enables G30. CFIA-P activates G30

the Program Maintenance Panel is touched,

causing IFAD-N to go low which sets FF10.

operation is similar to when the halt switch

The output of FF10 is inverted by Ill which

is touched, except FRDR-N goes low and

causes the done LED (CR57) to light. FF10

FRDS-P goes high. When FRDR-N goes low

remains set until another master reset

G54 is activated which activates G55. The

pulse, MRES-N, is received or until FSBS-P

output of G55 is inverted by I23 which en-

is generated again which will only occur

ables G56. When FWlS-P (waveform L,

with another switch closure on the Program

figure 108) goes high, G56 is activated

Maintenance Panel switch flip-flops and

causing ARAB-P to go high. With ARAB-P

single action discriminator circuit.. The

and CRAB-N high the address determined

next positive going edge out of I3 triggers

by the address switches is strobed to the

state generator U34, causing FSDS-P to go

INFIBUS address lines when INFIBUS ac-

Pow and FSDR-N to go high. Because state

cess is gained. With RNDB-P, VADB-P,

generator U34 is in its quiescent state (all

and HTDB-P low and DRDB-N high, no

outputs Pow) all operations in the Program

information (zero address) is strobed to

Maintenance Panel state generation and

FIBUS data lines when INFIBUS ac-

micro operations circuit cease until OSTS-P

ccss IS gained and the device addressed

is generated by another switch closure in

(slave) places its data on the INFIBUS

the Program Maintenance Panel switch

data lines. This data is displayed by the

flip-flops and single action discriminator

circuit, an address halt is required, or an

data 0 through 15 LEDS in the Program

address recognition occurs.

5-708. When the address write switch on

the Program Maintenance Panel switch

flip-flops and single action discriminator

is touched, operation is the same as when

the halt switch is touched, except FWRR-N

goes low and FWRS-P goes high. When

FWRR-N goes low, gates G53 and G54 are

activated. The output of G54 activates

gate G55. The output of G55 is inverted

by inverter I23 which enables gate G56.

The output of G53 enables gate G52. When

FW1S-P goes high, G52 and G56 are acti-

vated causing DRDB-N to go low and

ARAB-P to go hi

With ARAB-P and

CRAB-N high, t address determined

by the address switches is strobed to

US address lines when

5-110